在Verilog中,可以使用状态机的方法实现跑马灯程序。下面是一个简单的例子:
module horse_lamp (
input clk,
output reg [3:0] lamp
);
enum {S1, S2, S3, S4} state;
always @(posedge clk) begin
case (state)
S1: lamp = 4'b0001;
if (lamp == 4'b0001) begin
state <= S2;
end
S2: lamp