AT32F435/F437 QSPI驱动华邦/恒烁 NAND FLASH(W25N01G/ZB35Q01A)

黑色HS

已于 2023-07-13 22:17:35 修改

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分类专栏： Artery 文章标签：单片机嵌入式硬件 nand flash ZB35Q01 W25N01G

于 2023-07-11 10:26:33 首次发布

本文链接：https://blog.csdn.net/weixin_38933763/article/details/130941048

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好记性不如烂笔头，既然不够聪明，就乖乖的做笔记，温故而知新。

本文档用于本人对知识点的梳理和记录

一、前言

(ST生态)雅特力AT32F435/F437 QSPI驱动NAND FLASH(W25N01G/ZB35Q01A)
SPI驱动NAND FLASH比较常见，QSPI驱动NAND FLASH截至目前没有未看到太多博客，调试中也遇到一些坑，本例程也许可避免你少走弯路。

二、器件分析

NAND FLASH的特点就不赘述了，度娘大把，这里需要注意的是NAND不能直接寻址，最小的擦除单位是block，最小的读写单位是page，以1G的W25N01或ZB35Q01A为例，1个block包含64个page，一个page 2K byte，除此之外它的cache是2K，大小同最小读写单位。

因此，在操作flash的时候需要按下图示的方法执行

RA [16：6]bit 表示是block的地址；

RA [5：0]bit 表示是page的地址，64个page是不是刚好是[5：0]；

CA [11：0] 共12个bit，表示的是从cache中读出数据的起始位

三、代码分析

a、按AT32F435 DS和RM手册配置合适的PIN脚

void qspi_config(void)
{
  gpio_init_type gpio_init_struct;
  /* enable the dma clock */
  crm_periph_clock_enable(CRM_DMA2_PERIPH_CLOCK, TRUE);

  /* enable the qspi clock */
  crm_periph_clock_enable(CRM_QSPI1_PERIPH_CLOCK, TRUE);

  /* enable the pin clock */
  crm_periph_clock_enable(CRM_GPIOF_PERIPH_CLOCK, TRUE);
  crm_periph_clock_enable(CRM_GPIOG_PERIPH_CLOCK, TRUE);

  /* set default parameter */
  gpio_default_para_init(&gpio_init_struct);

  /* configure the io0 gpio */
  gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  gpio_init_struct.gpio_out_type  = GPIO_OUTPUT_PUSH_PULL;
  gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  gpio_init_struct.gpio_pins = GPIO_PINS_8;
  gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  gpio_init(GPIOF, &gpio_init_struct);
  gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE8, GPIO_MUX_10);

  /* configure the io1 gpio */
  gpio_init_struct.gpio_pins = GPIO_PINS_9;
  gpio_init(GPIOF, &gpio_init_struct);
  gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE9, GPIO_MUX_10);

  /* configure the io2 gpio */
  gpio_init_struct.gpio_pins = GPIO_PINS_7;
  gpio_init(GPIOF, &gpio_init_struct);
  gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE7, GPIO_MUX_9);

  /* configure the io3 gpio */
  gpio_init_struct.gpio_pins = GPIO_PINS_6;
  gpio_init(GPIOF, &gpio_init_struct);
  gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE6, GPIO_MUX_9);

  /* configure the sck gpio */
  gpio_init_struct.gpio_pins = GPIO_PINS_10;
  gpio_init(GPIOF, &gpio_init_struct);
  gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE10, GPIO_MUX_9);

  /* configure the cs gpio */
  gpio_init_struct.gpio_pins = GPIO_PINS_6;
  gpio_init(GPIOG, &gpio_init_struct);
  gpio_pin_mux_config(GPIOG, GPIO_PINS_SOURCE6, GPIO_MUX_10);
}

b、配置QSPI时钟和模式等，再尝试读取feature(SR状态寄存器)，读取成功，说明QSPI通信正常，需要注意的是，需按规格书要求配置QSPI的时序。

uint8_t qspi_data_get_featrue(uint32_t addr)
{
  uint8_t buf;
  /* config qspi's dma mode */
  qspi_dma_enable(QSPI1, TRUE);
  qspi_dma_rx_threshold_set(QSPI1, QSPI_DMA_FIFO_THOD_WORD08);

  /* config and enable dma */
  qspi_dma_set_byte(DMA_DIR_PERIPHERAL_TO_MEMORY, (uint8_t *)&buf, 1);

  /* kick command */
  esmt32m_cmd_get_featrue_config(&esmt32m_cmd_config, addr, 1);
  qspi_cmd_operation_kick(QSPI1, &esmt32m_cmd_config);

  /* wait command completed */
  while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET);
  qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG);

  /* wait dma completed */
  while(dma_flag_get(DMA2_FDT1_FLAG) == RESET);
  dma_flag_clear(DMA2_FDT1_FLAG);
  qspi_dma_enable(QSPI1, FALSE);

  return buf;
}

void esmt32m_cmd_get_featrue_config(qspi_cmd_type *qspi_cmd_struct, uint32_t addr, uint32_t counter)
{
  qspi_cmd_struct->pe_mode_enable = FALSE;
  qspi_cmd_struct->pe_mode_operate_code = 0;
  qspi_cmd_struct->instruction_code = 0x0F;
  qspi_cmd_struct->instruction_length = QSPI_CMD_INSLEN_1_BYTE;
  qspi_cmd_struct->address_code = addr;
  qspi_cmd_struct->address_length = QSPI_CMD_ADRLEN_1_BYTE;
  qspi_cmd_struct->data_counter = counter;
  qspi_cmd_struct->second_dummy_cycle_num = 0;
  qspi_cmd_struct->operation_mode = QSPI_OPERATE_MODE_111;
  qspi_cmd_struct->read_status_config = QSPI_RSTSC_HW_AUTO;
  qspi_cmd_struct->read_status_enable = FALSE;
  qspi_cmd_struct->write_data_enable = FALSE;
}

c、读取设备ID进一步验证通信和设备正常工作。

#if APP_CONFIG_NAND_ZB35Q01
  qspi_data_read_ID(0,1,(uint8_t *)&rbuf_id);
  printf("id msb=%x\r\n",rbuf_id);
  qspi_data_read_ID(1,1,(uint8_t *)&rbuf_id);
  printf("id lsb=%x\r\n",rbuf_id);
#elif APP_CONFIG_NAND_W25N01G
  qspi_data_read_ID(0,3,rbuf_id);
  printf("id lsb=%x\r\n",rbuf_id[1]);
#endif

d、以读为例，先将数据读出到cache，再从cache读出

void qspi_data_read_nand(uint16_t BlockAddr,uint8_t Pageuint16_tAddr,uint8_t wrap_flag, uint16_t r_addr, uint32_t total_len, uint8_t* buf)
{
  uint32_t addr;

  addr = ((uint32_t)BlockAddr << 6) + Pageuint16_tAddr;

  /* kick command */
  esmt32m_cmd_proread_nand_config(&esmt32m_cmd_config, addr, 0);
  qspi_cmd_operation_kick(QSPI1, &esmt32m_cmd_config);

  /* wait command completed */
  while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET);
  qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG);

  qspi_busy_check();

  qspi_data_read_nand_cache(wrap_flag,r_addr, total_len, buf);
}

void esmt32m_cmd_proread_nand_config(qspi_cmd_type *qspi_cmd_struct, uint32_t addr, uint32_t counter)
{
  qspi_cmd_struct->pe_mode_enable = FALSE;
  qspi_cmd_struct->pe_mode_operate_code = 0;
  qspi_cmd_struct->instruction_code = 0x13;
  qspi_cmd_struct->instruction_length = QSPI_CMD_INSLEN_1_BYTE;
  qspi_cmd_struct->address_code = addr;
  qspi_cmd_struct->address_length = QSPI_CMD_ADRLEN_3_BYTE;
  qspi_cmd_struct->data_counter = 0;
  qspi_cmd_struct->second_dummy_cycle_num = 0;
  qspi_cmd_struct->operation_mode = QSPI_OPERATE_MODE_111;
  qspi_cmd_struct->read_status_config = QSPI_RSTSC_HW_AUTO;
  qspi_cmd_struct->read_status_enable = FALSE;
  qspi_cmd_struct->write_data_enable = TRUE;
}

void qspi_data_read_nand_cache(uint8_t wrap_flag, uint16_t addr, uint32_t total_len, uint8_t* buf)
{
  uint16_t app_addr;

  app_addr = (((uint16_t)wrap_flag << 14) | addr); 

  /* config qspi's dma mode */
  qspi_dma_enable(QSPI1, TRUE);
  qspi_dma_rx_threshold_set(QSPI1, QSPI_DMA_FIFO_THOD_WORD08);

  /* config and enable dma */
  qspi_dma_set(DMA_DIR_PERIPHERAL_TO_MEMORY, buf, total_len);

  /* kick command */
  esmt32m_cmd_read_nand_cache_config(&esmt32m_cmd_config, app_addr, total_len);
  qspi_cmd_operation_kick(QSPI1, &esmt32m_cmd_config);

  /* wait command completed */
  while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET);
  qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG);

  /* wait dma completed */
  while(dma_flag_get(DMA2_FDT1_FLAG) == RESET);
  dma_flag_clear(DMA2_FDT1_FLAG);
  qspi_dma_enable(QSPI1, FALSE);
}

e、通过先写后读，以及擦除等步骤，验证数据存取正常

  printf("start read nand\r\n");
  /* program */
  qspi_data_write_nand(WRITE_CACHE_ADDR, WRITE_NAND_BLOCK, WRITE_NAND_PAGES,TEST_SIZE, wbuf);

  qspi_data_read_nand(READ_NAND_BLOCK, READ_NAND_PAGES,READ_NAND_WRAP,READ_CACHE_ADDR, TEST_SIZE, rbuf);

  nand_flash_printf(rbuf);

  printf("nand flash work end\r\n");

#if APP_CONFIG_ERASE_TEST_MODE
  printf("erase start!\r\n");
  qspi_erase_nand(READ_NAND_BLOCK,READ_NAND_PAGES);

  qspi_data_read_nand(READ_NAND_BLOCK, READ_NAND_PAGES,READ_NAND_WRAP,READ_CACHE_ADDR, TEST_SIZE, rbuf);
#endif

  if(memcmp(rbuf, wbuf, TEST_SIZE))
  {
    err = 1;
  }

f、通过 nand_flash_printf 将读出的数据打印出来，我们可以看到和预期的结果一致。

四、结语

好像也没啥难度，是吗？

有问题可以Email交流 495323976@qq.com

黑色HS

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AT32F435/F437 QSPI驱动华邦/恒烁 NAND FLASH(W25N01G/ZB35Q01A)

(ST生态)雅特力AT32F435/F437 QSPI驱动NAND FLASH(W25N01G/ZB35Q01A)SPI驱动NAND FLASH比较常见，QSPI驱动NAND FLASH截至目前没有未看到太多博客，调试中也遇到一些坑，本例程也许可避免你少走弯路。好像也没啥难度，是吗？有问题可以Email交流 495323976@qq.com。
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