verilog snippets for vscode

//verilog snippets for vscode
{
	// Place your global snippets here. Each snippet is defined under a snippet name and has a scope, prefix, body and 
	// description. Add comma separated ids of the languages where the snippet is applicable in the scope field. If scope 
	// is left empty or omitted, the snippet gets applied to all languages. The prefix is what is 
	// used to trigger the snippet and the body will be expanded and inserted. Possible variables are: 
	// $1, $2 for tab stops, $0 for the final cursor position, and ${1:label}, ${2:another} for placeholders. 
	// Placeholders with the same ids are connected.
	// Example:
	// "Print to console": {
	// 	"scope": "javascript,typescript",
	// 	"prefix": "log",
	// 	"body": [
	// 		"console.log('$1');",
	// 		"$2"
	// 	],
	// 	"description": "Log output to console"
	// }

	 "Print verilog header to console": {
	// 	"scope": "verilog, systemverilog",
	 	"prefix": "header",
	 	"body": [
			"//------------------------------------------------------------------",
			"// COPYRIGHT (c) Ericsson China, 2014                               ",
			"// The copyright to the document(s) herein is the property of",
			"// Ericsson China.",
			"//",
			"// The document(s) may be used and/or copied only with the written",
			"// permission from Ericsson China, or in accordance with",
			"// the terms and conditions stipulated in the agreement/contract",
			"// under which the document(s) have been supplied.",
			"//",
			"// All rights reserved.",
			"//------------------------------------------------------------------",
			"//",
			"// Author: enrsuwg (liang.chang@ericsson.com)",
			"// Created: $CURENT_YEAR-$CURRENT_MONTH-$CURRENT_DATE",
			"//",
			"//------------------------------------------------------------------",
			"// Description:",
			"//  ${1:add context} ",
			"//------------------------------------------------------------------"
	 	],
	 	"description": "Log header to console"
	 }

	"Print sv alwasys_ff to console": {
			// 	"scope": "verilog, systemverilog",
		"prefix": "alwaysff",
		"body": [
			"always @(posedge ${1:clk})",
			"  begin",
			"    if(${2:rst})",
			"      begin",
			"        $3 <= '0; ",
			"      end",
			"    else if(${4:condition0})", 
			"      begin",
			"	     $3 <= '1;		  ",
			"      end",
			"    else if(${5:condition1})", 
			"      begin",
			"	     $3 <= '0;		  ",
			"      end",
			"    else ",
			"	   begin",
			"	     $3 <= $3;",
			"	   end",
			"  end"
		],
		"description": "alwaysff to console"
	 }




	"Print verilog FSM3 to console": {
			// 	"scope": "verilog, systemverilog",
		"prefix": "fsm3",
		"body": [
            "//---------------------FSM State-----------------------------------------",
            "reg  [3:0]              state_c             ;",
            "reg  [3:0]              state_n             ;",
            "//---------------------FSM Parameter-------------------------------------",
            "localparam S0           = 4'b0001           ;",
            "localparam S1           = 4'b0010           ;",
            "localparam S2           = 4'b0100           ;",
            "localparam S3           = 4'b1000           ;",
            "                                                           ",
            "//----------------------------------------------------------------------",
            "//--   FSM first part",
            "//----------------------------------------------------------------------",
            "always @(posedge clk)begin",
            "    if(rst)",
            "        state_c <= S0;",
            "    else",
            "        state_c <= state_n;",
            "end",
            "                                               ",
            "//----------------------------------------------------------------------",
            "//--   FSM second part",
            "//----------------------------------------------------------------------",
            "always @(*)begin",
            "    case(state_c)                                                   ",
            "        S0: begin",
            "            if(in==1)",
            "                state_n = S1;",
            "            else if(in==2)",
            "                state_n = S2;",
            "            else",
            "                state_n = state_c;",
            "        end",
            "        S1: begin",
            "            if(in==1)",
            "                state_n = S2;",
            "            else if(in==2)",
            "                state_n = S3;",
            "            else",
            "                state_n = state_c;",
            "        end",
            "        S2: begin",
            "            if(in==1)",
            "                state_n = S3;",
            "            else if(in==2)",
            "                state_n = S0;",
            "            else",
            "                state_n = state_c;",
            "        end",
            "        S3: begin",
            "            if(in==1 || in==2)      // in != 0",
            "                state_n = S0;",                                           
            "            else                                                          ",
            "                state_n = state_c;",
            "        end",
            "        default:state_n = S0;",
            "    endcase",
            "end",
            "                                                                      ",
            "//----------------------------------------------------------------------",
            "//--   FSM third part",
            "//----------------------------------------------------------------------",
            "                                                                 ",
            "always @(posedge clk)begin",
            "    if(rst)",
            "        out <= 0;",
            "    else if(state_c==S3 && in==2)",
            "        out <= 1;",
            "    else",
            "        out <= 0;",
            "end",
            "                                                                           ",
            "always @(posedge clk)begin",
            "    if(rst)",
            "        out_vld <= 0;",
            "    else if((state_c==S2 && in==2) || (state_c==S3 && in!=0))",
            "        out_vld <= 1;",
            "    else",
            "        out_vld <= 0;",
            "end"

		]
		"description": "verilog fsm3 to console"
	}

	"print sv delay": {	
		"prefix": "print delay",
		"body": [
			"logic [3:0] ${1:data}_d1, ${1:data}_d2, ${1:data}_d3;",
			"                      ",
			"always_ff @(posedge clk) begin",
			"  ${1:data}_d1 <= ${1:data};",
		    "  ${1:data}_d2 <= ${1:data}_d1;",
			"  ${1:data}_d3 <= ${1:data}_d2;",
			"end"
		]
		"description": "print sv delay"
    }

	"print sv module to console": {
		"prefix": "module",
		"body": [
			"module $TM_FILENAME_BASE",
			"#(",
			"	parameter C_ = $1",
			")",
			"(",
			"	input logic clk,",
			"	input logic rst,",
			"	input logic in,",
			"	input logic out",
			"		",
			");",
			"		",
			"		",
			"		",
			"endmodule"
		]
		"description": "print sv module to console"
    }
}