文章目录
1. “General Purpose” Processors
It would be highly desirable if the same hardware could execute program written in Python,Java,C or any high-level language.
It is also not sensible to execute every feature of a high-level language directly in hardware
2. Components of a Microprocessor
- Each register is of fixed size,say 32 bits
- The number of registers are small,say 32
- ALU directly perform operations on the register file,typically ·x_i <- Op(x_j,x_k) where Op∈{+,AND,OR,<,>,…}
- Memory is large,say Giga bytes,and hold program and data
- Data can be moved back and forth between Memory and Register File using load and store instructions
3. Assembly Language Program
An assembly Language Program is a sequence of instructions which execute in a sequential order unless a control instruction is to be executed.
Each instruction specifies a operation supported by the processor hardware
- ALU
- Load and Store
- Control Transfer:e.g. if x_i < x_j go to label l
4. Program to sum array elements
sum = a[0] + a[1] + a[2] + … + a[n-1]
x1 <- load(base) //load data from main memory to register x1
x2 <- load(n) //load data from main memory to register x2
x3 <- 0 //let register x3 = 0
loop: //sign for repeating
x4 <- load(Mem[x1]) //load data from main Mem[x1] to register x4
add x3, x3, x4 //ALU arithmetic:data of x3 plus data of x4 and assign the sum to regeister x3
addi x1, x1, 4 //ALU arithmetic:data of x1 plus 4 and assign the sum to regeister x1
addi x2, x2, -1 //ALU arithmetic:data of x2 plus -1 and assign the sum to regeister x2
//bnez(Branch if Not Equal to Zero)
bnez x2, loop //if data(x2) != 0,retuen to the foregoing loop and excute again
store(sum) <- x3 //store data form register x3 to main Memory sum
5. Instruction Set Architecture(ISA)
- ISA:The contract between software and hardware
- Functional definition of operations and storage locations
- Precise description of how software can invoke and access them
- RISC-V ISA:
- A new,open,free ISA from berkeley
- A new,open,free ISA from berkeley
6. RISC-V Processor Storage
7. Instructions
Three Types of operations:
- Computational
- Loads and Stores
- Control Flow
7.1 register-register instructions
- 2 source operand registers
- 1 destination register
- format: oper dest,src1,src2
7.2 register-immediate instructions
- 1 source operand register
- a small constant that is encoded into the instruction
- format:oper dest,src1,const
7.3 LUI
load upper immediate
consider about register-immediate instructions,we can only operate 12bits constant.supposing getting constants that are larger than 12 bits into register,we use lui instruction to get it.
lui x2,0x3 //x2 = 0x30000
lui x2,0xffff //x2 = 0xffff0000
//every unsigned number bigger than 0xffff will take an overflow
7.4 Control Flow Instructions
Need Conditional Branch Instructions
Unconditional Control Instructions
Problem:what is the function of x3(dest)?
7.5 RISC-V Load and Store Instructions
- Address is specified as a <base address,offset> pair;
- base address is always stored in register;
- the offset is encoded as a 12 bit constant in the instruction
- Format:
lw dest,offset(base) sw src,offset(base)
Program to Sum Array Elements Ⅱ
sum = a[0] + a[1] + … + a[n-1]
lw x1,0x0(x10) //base = 100 and offset = 0
lw x2,0x4(x10) //base = 100 and offset = 4
add x3,x0,x0 //x0 is presupposed zero
loop:
lw x4,0x0(x1) //load word a[n]
add x3,x3,x4 //arithmatic in ALU
addi x1,x1,4 //change the address pointer of x1 to a[n + 1]
addi x2,x2,-1 //use x2 to control the loop times
bnez x2,loop //jump to the first loop if x2 is not equal to zero
sw x3, 0x8(x10) //save sum in memory at address 108
7.6 Pseudoinstructions
Purpose:Simply assembly programming