Introduction to Assembly and RISC-V

1. “General Purpose” Processors

在这里插入图片描述
It would be highly desirable if the same hardware could execute program written in Python,Java,C or any high-level language.
It is also not sensible to execute every feature of a high-level language directly in hardware

2. Components of a Microprocessor

  1. Each register is of fixed size,say 32 bits
  2. The number of registers are small,say 32
  3. ALU directly perform operations on the register file,typically ·x_i <- Op(x_j,x_k) where Op∈{+,AND,OR,<,>,…}
  4. Memory is large,say Giga bytes,and hold program and data
  5. Data can be moved back and forth between Memory and Register File using load and store instructions
    在这里插入图片描述

3. Assembly Language Program

An assembly Language Program is a sequence of instructions which execute in a sequential order unless a control instruction is to be executed.
Each instruction specifies a operation supported by the processor hardware

  1. ALU
  2. Load and Store
  3. Control Transfer:e.g. if x_i < x_j go to label l

4. Program to sum array elements

sum = a[0] + a[1] + a[2] + … + a[n-1]
在这里插入图片描述

x1 <- load(base) 	//load data from main memory to register x1
x2 <- load(n)    //load data from main memory to register x2
x3 <- 0                 //let register x3 = 0
loop:                   //sign for repeating
x4 <- load(Mem[x1])     //load data from main Mem[x1] to register x4
add x3, x3, x4          //ALU arithmetic:data of x3 plus data of x4 and assign the sum to regeister x3
addi x1, x1, 4          //ALU arithmetic:data of x1 plus 4 and assign the sum to regeister x1
addi x2, x2, -1         //ALU arithmetic:data of x2 plus -1 and assign the sum to regeister x2
//bnez(Branch if Not Equal to Zero)
bnez x2, loop           //if data(x2) != 0,retuen to the foregoing loop and excute again
store(sum) <- x3        //store data form register x3 to main Memory sum

在这里插入图片描述

5. Instruction Set Architecture(ISA)

  • ISA:The contract between software and hardware
    • Functional definition of operations and storage locations
    • Precise description of how software can invoke and access them
  • RISC-V ISA:
    • A new,open,free ISA from berkeley
      在这里插入图片描述

6. RISC-V Processor Storage

在这里插入图片描述

7. Instructions

Three Types of operations:

  • Computational
  • Loads and Stores
  • Control Flow

7.1 register-register instructions

  • 2 source operand registers
  • 1 destination register
  • format: oper dest,src1,src2

7.2 register-immediate instructions

  • 1 source operand register
  • a small constant that is encoded into the instruction
  • format:oper dest,src1,const
    在这里插入图片描述

7.3 LUI

load upper immediate

consider about register-immediate instructions,we can only operate 12bits constant.supposing getting constants that are larger than 12 bits into register,we use lui instruction to get it.

lui x2,0x3             //x2 = 0x30000
lui x2,0xffff         //x2 = 0xffff0000
//every unsigned number bigger than 0xffff will take an overflow

7.4 Control Flow Instructions

Need Conditional Branch Instructions

在这里插入图片描述

Unconditional Control Instructions

在这里插入图片描述
Problem:what is the function of x3(dest)?

7.5 RISC-V Load and Store Instructions

  • Address is specified as a <base address,offset> pair;
    • base address is always stored in register;
    • the offset is encoded as a 12 bit constant in the instruction
    • Format: lw dest,offset(base) sw src,offset(base)
      在这里插入图片描述
Program to Sum Array Elements Ⅱ

sum = a[0] + a[1] + … + a[n-1]
在这里插入图片描述

lw x1,0x0(x10) //base = 100 and offset = 0 
lw x2,0x4(x10) //base = 100 and offset = 4
add x3,x0,x0   //x0 is presupposed zero

loop:
lw x4,0x0(x1) //load word a[n]
add x3,x3,x4  //arithmatic in ALU
addi x1,x1,4  //change the address pointer of x1 to a[n + 1]
addi x2,x2,-1 //use x2 to control the loop times
bnez x2,loop  //jump to the first loop if x2 is not equal to zero

sw x3, 0x8(x10) //save sum in memory at address 108

7.6 Pseudoinstructions

Purpose:Simply assembly programming
在这里插入图片描述

  • 1
    点赞
  • 0
    收藏
    觉得还不错? 一键收藏
  • 0
    评论
The objective of this book is to introduce assembly language programming. Assembly language is very closely linked to the underlying processor architecture and design. Popular processor designs can be broadly divided into two categories: Complex Instruction Set Computers (CISC) and Reduced Instruction Set Computers (RISC). The dominant processor in the PC market, Pentium, belongs to the CISC category. However, the recent design trend is to use the RISC designs. Some example RISC processors include the MIPS, SPARC, PowerPC, and ARM. Even Intel’s 64-bit processor Itanium is a RISC processor. Thus, both types of processors are important candidates for our study. This book covers assembly language programming of both CISC and RISC processors. We use the Intel Pentium processor as the representative of the CISC category. We have selected the Pentium processor because of its market dominance. To explore RISC assembly language, we selected the MIPS processor. The MIPS processor is appealing as it closely adheres to the RISC principles. Furthermore, the availability of the SPIM simulator allows us to use a Pentium-based PC to learn MIPS assembly language. New in the Second Edition The second edition has been substantially revised to reflect the changes that have taken place since the publication of the first edition. The major changes are listed below: . We introduced RISC assembly language programming so that the reader can benefit from learning both CISC and RISC assembly languages. As mentioned before, Pentium and MIPS processors are used to cover CISC and RISC processors. . The first edition used MASM/TASM assemblers. In this edition, we use the NASM assembler. The syntax of NASM is slightly different from that of MASM/TASM assemblers. The advantage is that NASM is free! Another advantage is that it works with both MicrosoftWindows and Linux operating systems. . Consistent with our shift to NASM, we moved away from DOS to Linux. Since NASM is available for Windows a

“相关推荐”对你有帮助么?

  • 非常没帮助
  • 没帮助
  • 一般
  • 有帮助
  • 非常有帮助
提交
评论
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值