A Detailed Instruction to a Subset of RISC-V Instructions

1. Computational Instrucitions

1.1 R-type:register-register instructions

• opcode = OP = 0110011

Arithmetic	Comparisons	Logical	Shifts
ADD,SUB	SLT,SLTU	AND,OR,XOR	SLL,SRL,SRA

• Assembly instr: oper rd,rs1,rs2
• Behavior: reg[rd] <= reg[rs1] oper reg[rs2]

Operator	Complete representation
SLT	Set less than
SLTU	Set less than unsigned
SLL	Shift left logical
SRL	Shift right logical
SRA	Shift right arithmetic

1.2 I-type:Register immediate instructions

opcode = OP-IMM = 0010011

Arithmetic	Comparisons	Logical	Shifts
ADDI	SLTI,SLTIU	ANDI,ORI,XORI	SLLI,SRLI,SRAI

• Assembly instr: opr rd,rs,immI
• Behavior: imm = signExtend(immI) reg[rd] <= reg[rs1] opr imm

1.3 U-type

• opcode = LUI OR AUIPC =(01|00)10111
• Assembly instr: lui rd,immU
• Behavior: imm = {immU,12’b0} Reg[rg] <= imm
• immU is a 20 bit constant

Operator	Complete Representation
LUI	Load Upper Immediate
AUIPC	Add Upper Immediate to PC

2. Load Store Instructions

2.1 I-type

• Load:with operator = LOAD = 0000011
• Assembly instr: lw rd,immI(rs1)
• Behavior:imm = signExtend(immI) Reg(rd) <= Mem[Reg(rs1) + imm]

Operator	Complete Representation
LW	Load Word

2.2 S-type

• Store:with operator = STORE = 0100011
• Assembly instr: sw rs2,immS(rs1)
• Behavior:imm = signExtend(immS) Mem[Reg[rs1] + imm] <= Reg[rs2]

Operator	Complete Representation
SW	Save Word

3. Control Instructions

3.1 SB-type

• Conditional Branches: opcode = 110011
• Assembly instr: oper r1,r2,label
• Behavior:imm = distance to label in bytes = {immS[12:1],0} pc <= (R[rs1] comp R[rs2] ? pc + imm:pc + 4)
• Compares register rs1 to rs2. If comparison is true then pc is updated with pc + imm, otherwise pc becomes pc + 4. Comparison type is defined by operation.

Operator	Complete Representation
BEQ	branch if equal
BNE	branch if not equal (!=)
BLT	branch if less than (<)
BGE	branch if greater than or equal (>=)
BLTU	branch if less than using unsigned numbers (< unsigned)
BGEU	branch if greater than or equal using unsigned numbers (>= unsigned)

3.2 UJ-type

3.2.1 JAL

• Unconditional Jump
• opcode = JAL = 1101111
• Assembly instr: JAL rd,label
• Behavior:imm = distance to label in bytes = {immU{20:1},0} pc[rd] <= pc + 4; pc <= pc + imm
• Promblem:what is the structure of pc?what is pc[rd]?

3.2.2 I-type JAL

• Unconditional Jump
• opcode = JALR = 1100111
• Behavior: imm = SignExtend(immI) pc[rd] <= pc + 4; pc <= (R[rs1]+imm) & ~0x01
• (zero out the bottom bit of pc)
  
  -Problem:I can’t understand the behavior of JALR

Operator	Complete Representation
JAL	jump and link
JALR	jump and link register

4. Common Pseudoinstructions

Pseudoinstruction	Equivalent Assembly Instruction
j label	jal x0, label (ignore return address)
li x1, 0x1000	lui x1, 1
li x1, 0x1100	lui x1, 1; addi x1, x1, 0x100
li x4, 3	addi x4, x0, 3
mv x3, x2	addi x3, x2, 0
beqz x1, target	beq x1, x0, target
bneqz x1, target	bneq x1, x0, target

5. Reference Card