PYNQ手册原理图管脚等
http://www.tul.com.tw/productspynq-z2.html
PL使用
当做zynq的FPGA单独使用,verilog语言
micro USB下载,跳线换成JTAG启动
工程里加上PYNQ的boardfile
PYNQ管脚约束
加source file
code
流水灯
`timescale 1ns / 1ps
module PL_LED_TEST(
input clk,
input rst,
output reg [3:0]LED
);
parameter CNT_LEN = 4;
reg [25:0] cntr ;
reg [1:0] cnt4 ;
always @ (posedge clk)
if ( rst ) cntr<=0;
else if(cntr==49_999_999)
cntr<=0;
else
cntr <=cntr+1 ;
always @ (posedge clk)
if ( rst ) cnt4<=0;
else if(cntr==49_999_999)
if(cnt4==3)
cnt4<=0;
else
cnt4 <=cnt4+1 ;
always @ (posedge clk)
if ( rst ) L