matlab fmaxbnd,Fmax定义及推导

时序分析之fmax定义及推导

2011-11-19 01:20

时钟是一个电路的心脏和节拍器，学习时序分析当然要从时钟周期(时钟频率)开始了，时序约束主要是为了满足器件稳定工作在我们需要的工作频率！！！ 以前对频率的理解很简单，认为晶振输入多少就是多少工作频率，可是现在才认识到FPGA器件在设计出功能后，因为器件内部的各种延迟，数据的采集、建立和传输都有时间延迟，如果时钟周期小于这个延迟，则芯片内部的数据在当前时钟还没有正常的采集、建立和传输，下一个时钟就已经来到，造成工作错乱——这就是电路能承受的最高工作频率，如果要求工作在100MHz ，但是电路只能跑到80MHz，如果硬是上到100MHz的输入频率，那么这个芯片由于不满足时序将不能正常工作，下面是Quartus II官方的fmax定义：

The maximum clock frequency that can be achieved without violating internal setup (tSU) and hold (tH) time requirements. Unrestricted fMAX is the maximum frequency at which a design can run. Restricted fMAX is the maximum frequency a design can run considering device limits, such as maximum toggle rates. The Classic Timing Analyzer analyzes and reports fMAX following timing analysis.

You can specify the fMAX required by default for a design in

the Classic Timing Analysis Settings page of the Settings dialog box. You can also specify the required fMAX of individual clock signals in a design by creating clock settings and assigning them to signals in the design.

The Classic Timing Analyzer calculates fMAX with the following equation: fMAX=1/(- + + )

简化公式就是：fmax=1/(data delay+Tsu+Tco -clock skew)

Clock skew delay is calculated with the following equation:

简化公式就是：clock skew=Tc2d-Tc2s

下面看看这个fmax是怎么计算出来的，Quartus II标准周期定义按下图计算：