e几个灯同时亮灭两次verilog_求verilog编程 按下按键相应灯亮 按下同一按键相应灯灭 按下其他按键相应灯轮流亮...

展开全部

module jishiqi (smg_dx,smg_wx,clk,reset_key0,clr_key1);

input clk,reset_key0,clr_key1;

wire reset_key0_in,clr_key1_in;

output[7:0] smg_dx;

output[3:0] smg_wx;

reg bian_liang1=1,bian_liang2=1,bian_liang3=1,fp_1ms;

reg[1:0] wx,data_wx;

reg[3:0] smg_wx1,data_dx,miao_10ms,miao_100ms,miao,miao_shiwei,reset_key0_out,clr_key1_out;

reg[7:0] smg_dx1,dx;

reg[15:0] data;

reg[31:0] count,sum;

always @ (posedge clk)

begin

begin

if(count==25_000)

begin

count<=0;

fp_1ms<=~fp_1ms;

end

else count<=count+1;

end

begin

if(!reset_key0_in)

begin

bian_liang1<=~bian_liang1;

end

else if(bian_liang1==0)

begin

miao_10ms<=0;

miao_100ms<