https://www.stmcu.org.cn/document/download/index/id-212351
论坛就有呀,你搜索"coremark",就有如何将coremark程序移植到STM32上.pdf
下面是测试结果.
----------------------------------------------------
Config.: 1 - Exec in Ram ITCM - Data in DTCM
----------------------------------------------------
System frequency: 200MHz
-------------------------------------------
| Flash WS | ART | D-cache | I-cache |
+-----------+---------+---------+---------+
| NA | OFF | OFF | OFF |
-------------------------------------------
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 11952016
Total time (secs): 11.952016
Iterations/Sec : 1004.014720
Iterations : 12000
Compiler version : uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05
Compiler flags : -O3 Otime
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0xd340
Correct operation validated. See readme.txt for run and reporting rules.
CoreMark 1.0 : 1004.014720 / uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05 -O3 Otime / STACK
----------------------------------------------------
Config.: 2 - Exec in Flash AXI - Data in DTCM
----------------------------------------------------
System frequency: 200MHz
-------------------------------------------
| Flash WS | ART | D-cache | I-cache |
+-----------+---------+---------+---------+
| 6 | OFF | OFF | ON |
-------------------------------------------
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 12156203
Total time (secs): 12.156203
Iterations/Sec : 987.150346
Iterations : 12000
Compiler version : uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05
Compiler flags : -O3 Otime
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0xd340
Correct operation validated. See readme.txt for run and reporting rules.
CoreMark 1.0 : 987.150346 / uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05 -O3 Otime / STACK
----------------------------------------------------
Config.: 3 - Exec in Flash AXI - Data in SRAM1
----------------------------------------------------
System frequency: 200MHz
-------------------------------------------
| Flash WS | ART | D-cache | I-cache |
+-----------+---------+---------+---------+
| 6 | OFF | ON | ON |
-------------------------------------------
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 12218410
Total time (secs): 12.218410
Iterations/Sec : 982.124515
Iterations : 12000
Compiler version : uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05
Compiler flags : -O3 Otime
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0xd340
Correct operation validated. See readme.txt for run and reporting rules.
CoreMark 1.0 : 982.124515 / uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05 -O3 Otime / STACK
----------------------------------------------------
Config.: 4 - Exec in Flash ITCM - Data in DTCM
----------------------------------------------------
System frequency: 200MHz
-------------------------------------------
| Flash WS | ART | D-cache | I-cache |
+-----------+---------+---------+---------+
| 6 | ON | OFF | OFF |
-------------------------------------------
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 12127302
Total time (secs): 12.127302
Iterations/Sec : 989.502859
Iterations : 12000
Compiler version : uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05
Compiler flags : -O3 Otime
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0xd340
Correct operation validated. See readme.txt for run and reporting rules.
CoreMark 1.0 : 989.502859 / uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05 -O3 Otime / STACK
----------------------------------------------------
Config.: 5 - Exec in External SRAM - Data in DTCM
----------------------------------------------------
System frequency: 200MHz
-------------------------------------------
| Flash WS | ART | D-cache | I-cache |
+-----------+---------+---------+---------+
| NA | OFF | OFF | ON |
-------------------------------------------
FMC SRAM config:
-----------------
| Mem Bus width |
+---------------+
| 16 |
-----------------
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 12984019
Total time (secs): 12.984019
Iterations/Sec : 924.213065
Iterations : 12000
Compiler version : uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05
Compiler flags : -O3 Otime
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0xd340
Correct operation validated. See readme.txt for run and reporting rules.
CoreMark 1.0 : 924.213065 / uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05 -O3 Otime / STACK
----------------------------------------------------
Config.: 6 - Exec in External SDRAM swapped - Data in DTCM
----------------------------------------------------
System frequency: 200MHz
-------------------------------------------
| Flash WS | ART | D-cache | I-cache |
+-----------+---------+---------+---------+
| NA | OFF | OFF | ON |
-------------------------------------------
FMC SDRAM config:
-----------------
| Mem Bus width |
+---------------+
| 32 |
-----------------
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 12325498
Total time (secs): 12.325498
Iterations/Sec : 973.591493
Iterations : 12000
Compiler version : uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05
Compiler flags : -O3 Otime
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0xd340
Correct operation validated. See readme.txt for run and reporting rules.
CoreMark 1.0 : 973.591493 / uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05 -O3 Otime / STACK
----------------------------------------------------
Config.: 7 - Exec in External SDRAM not swapped - Data in DTCM
----------------------------------------------------
System frequency: 200MHz
-------------------------------------------
| Flash WS | ART | D-cache | I-cache |
+-----------+---------+---------+---------+
| NA | OFF | OFF | ON |
-------------------------------------------
FMC SDRAM config:
-----------------
| Mem Bus width |
+---------------+
| 32 |
-----------------
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 64608165
Total time (secs): 64.608165
Iterations/Sec : 185.735038
Iterations : 12000
Compiler version : uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05
Compiler flags : -O3 Otime
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0xd340
Correct operation validated. See readme.txt for run and reporting rules.
CoreMark 1.0 : 185.735038 / uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05 -O3 Otime / STACK
----------------------------------------------------
Config.: 8 - Exec in QuadSPI Flash - Data in DTCM
----------------------------------------------------
System frequency: 200MHz
-------------------------------------------
| Flash WS | ART | D-cache | I-cache |
+-----------+---------+---------+---------+
| NA | OFF | OFF | ON |
-------------------------------------------
QSPI config:
| Prescaler | QSPI CLK | DDRMODE | Inst. lines nb |
+-----------+----------+---------+-----------------+
| 3 | 50MHz | ON | 1 |
----------------------------------------------------
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 14840884
Total time (secs): 14.840884
Iterations/Sec : 808.577171
Iterations : 12000
Compiler version : uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05
Compiler flags : -O3 Otime
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0xd340
Correct operation validated. See readme.txt for run and reporting rules.
CoreMark 1.0 : 808.577171 / uVision 5.12.00 - RealView MDK-ARM V5.12 - ARMCCV5.05 -O3 Otime / STACK