create_clock -period 25.000 -name clk_main [get_ports
DSIV_BYTE_CLK]
set_input_delay -clock [get_clocks *] 6 [get_ports
{DSIV_BCLK_EN DSIV_DO DSIV_HSYNC DSIV_VSYNC RESET}]
set_output_delay -clock [get_clocks *] 6 [get_ports -filter { NAME
=~ "*" && DIRECTION == "OUT" }]
set_property IOSTANDARD LVCMOS15 [get_ports
DSIV_BYTE_CLK]
set_property IOSTANDARD LVCMOS15 [get_ports DSIV_BCLK_EN]
set_property IOSTANDARD LVCMOS15 [get_ports DSIV_DO]
set_property IOSTANDARD LVCMOS15 [get_ports DSIV_HSYNC]
set_property IOSTANDARD LVCMOS15 [get_ports DSIV_VSYNC]
set_property IOSTANDARD LVCMOS15 [get_ports RESET]
set_property IOSTANDARD LVCMOS15 [get_ports
DSIV_8P_BCLK_EN]
set_property IOSTANDARD LVCMOS15 [get_ports pixel_count]
set_property IOSTANDARD LVCMOS15 [get_ports {DSIV_8P_DO[1]}]