verilog异步复位jk触发器_JK触发器(异步复位置位)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY jkff IS

PORT(clk,j,k,clr,pset:IN STD_LOGIC;

q,qb:OUT STD_LOGIC);

END jkff;

ARCHITECTURE behav1 OF jkff IS

SIGNAL q_s,qb_s:STD_LOGIC;

BEGIN

PROCESS(clk,pset,clr,j,k)

BEGIN

IF (clr=‘0’) THEN

q_s&lt=‘0’; qb_s&lt=‘1’;

ELSIF (pset=‘ 0’) THEN

q_s&lt=‘1’; qb_s&lt='0';

ELSIF (clk' event AND clk=' 1' ) THEN

IF (j=' 0' )AND(k=' 1' ) THEN

q_s&lt=' 0'; qb_s&lt=' 1';

ELSIF (j=' 1' )AND(k=' 0' ) THEN

q_s&lt=' 1'; qb_s&lt=' 0';

ELSIF (j=' 1' )AND (k=' 1' ) THEN

q_s&lt=NOT q_s; qb_s&lt=NOT qb_s；

END IF;

q&lt=q_s; qb&lt=qb_s；

END IF;

END PROCESS;

END behav;