HDLbits
文章平均质量分 77
verilog代码练习
FPGA终成恶龙
什么都学了一点,可是什么都不会。
展开
-
HDLbits9-Finite State Machines
15 Finite State Machines15.1 Simple FSM 1 (asynchronous reset)module top_module ( input clk, input areset, input in, output out ); parameter A = 1'b0, B = 1'b1; reg current_state,next_state; always @(posedge clk or posedge are原创 2022-05-02 16:37:53 · 279 阅读 · 0 评论 -
HDLbits答案8-Counters&Shift Registers&More Circuits
12 Counters12.1 Four-bit binary countermodule top_module ( input clk, input reset, output [3:0]q ); always@(posedge clk) if(reset) q <= 4'b0000; else if(q == 4'b1111) q <= 4'b0000; else q <= q+1'b1; endmodule原创 2022-04-09 17:25:13 · 268 阅读 · 0 评论 -
HDLbits答案7-Latches and Flip-Flops
11 Latcher and Flip-Flops11.1 D flip-flpsmodule top_module ( input clk, input d, output reg q ); always @(posedge clk) q <= d;endmodule11.2 D flip-flpsmodule top_module ( input clk, input [7:0]d, output reg [7:0]q );原创 2022-04-05 17:50:02 · 439 阅读 · 0 评论 -
HDLbits答案6-Multiplexers&Arithmetic Circuits&Karnaugh Map to Circuit
目录8 Multiplexers8.1 2-to-1 multiplexers8.2 2-to-1 bus multiplexers8.3 9-to-1 multiplexer8.4 256-to-1 multiplexer8.5 256-to-1 4-bit multiplexer9 Arithmetic Circuits9.1 Half adder9.2 Full adder9.3 3-bit binary adder9.4 Adder9.5 Signed原创 2022-04-04 20:27:26 · 300 阅读 · 0 评论 -
HDLbits答案5-Combinational Logic
7Basic Gates7.1wiremodule top_module(in,out); input in; output out; assign out=in; endmodule 7.2GNDmodule top_module(out); output out; assign out=1'b0; endmodule 7.3NORmodule top_module(in1,in2,out); input in1,in2; outp原创 2022-04-04 19:54:18 · 338 阅读 · 0 评论 -
HDLbits答案4
@[TOC]目录5.Procedure5.1 Always blocks(combinational)5.2 Always blocks(clocked)5.3 If statement5.4 If statement latches5.5 Case statement5.6 Priority encoder5.7 Priority encoder with casez5.8 Avoiding latches6.More Verilog Features6.1 Conditional原创 2021-04-11 21:16:58 · 406 阅读 · 0 评论 -
HDLbits答案3
目录4.层次结构4.1 模组4.2按位置连接端口4.3通过名称连接端口4.4三个模块4.5模块和向量4.6加法器14.7加法器24.8进位选择加法器4.9加减法4.1 模组4.2按位置连接端口4.3通过名称连接端口4.4三个模块4.5模块和向量4.6加法器14.7加法器24.8进位选择加法器4.9加减法4.层次结构4.1 模组4.2按位置连接端口4.3通过名称连接端口4.4三个模块4.5模块和向量4.6加法器14.7加法器24.8进位选择加法器4.9加减法4.1 模组module t原创 2021-03-26 16:45:35 · 197 阅读 · 0 评论 -
HDLbits答案2
@@TOC3.向量3.1向量3.2向量更详细3.3矢量零件选择3.4按位运算符3.5四输入门3.6向量串联运算符3.7矢量反转3.8复制运算符3.9更多复制3.1向量module top_module (vec,outv,o2,o1,o0);input wire [2:0]vec;output wire [2:0]outv;output o1,o2,o0;assign outv=vec;assign o2=vec[2];assign o1=vec[1];assign o原创 2021-03-26 16:34:31 · 227 阅读 · 0 评论 -
HDLbits答案1
目录1. 入门1.1 入门1.2 输出零2. 基本语言2.1 简易电路2.2 四线2.3 逆变器2.4 与门2.5 或非门2.6 XNOR门2.7 宣告电线2.8 7458芯片1.入门1.1 入门module top_module (one);output one;assign one=1’b1;endmodule1.2 输出零module top_module(zero);output zero;assign zero=1’b0;endmodule``2.原创 2021-03-16 16:40:25 · 450 阅读 · 0 评论