目录
11.5 DFF with asynchronous reset
11.14 Create circuit from truth table
11.19 Dual-edge triggered flip-flop
11 Latcher and Flip-Flops
11.1 D flip-flps
module top_module
(
input clk,
input d,
output reg q
);
always @(posedge clk)
q <= d;
endmodule
11.2 D flip-flps
module top_module
(
input clk,
input [7:0]d,
output reg [7:0]q
);
always @(posedge clk)
q <= d;
endmodule
11.3 DFF with reset
module top_module
(
input clk,reset,
input [7:0]d,
output reg [7:0]q
);
always @(posedge clk)
if(reset)
q <= 8'd0;
else
q <= d;
endmodule
11.4 DFF with reset value
module top_module
(
input clk,reset,
input [7:0]d,
output reg [7:0]q
);
always @(negedge clk)
if(reset)
q <= 8'h34;
else
q <= d;
endmodule
11.5 DFF with asynchronous reset
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk or posedge areset)
if(areset)
q <= 8'd0;
else
q <= d;
endmodule
11.6 DFF with byte enable
module top_module
(
input clk,resetn,
input [1:0]byteena,
input [15:0]d,
output reg [15:0]q
);
always @(posedge clk)
if(!resetn)
q <= 16'h0;
else begin
if(byteena[0])begin
if(byteena[1])
q <= d;
else
q <= {q[15:8],d[7:0]};
end
else begin
if(byteena[1])
q <= {d[15:8],q[7:0]};
else
q <= q;
end
end
endmodule
11.7 D latch
module top_module
(
input ena,d,
output q
);
always @(*)begin
if(ena)
q = d;
else
q = q;
end
endmodule
11.8 DFF
module top_module
(
input d,ar,clk,
output q
);
always @(posedge clk or posedge ar)begin
if(ar)
q = 1'b0;
else
q = d;
end
endmodule
11.9DFF
module top_module
(
input d,r,clk,
output q
);
always @(posedge clk)begin
if(r)
q = 1'b0;
else
q = d;
end
endmodule
11.10 DFF+gates
module top_module
(
input clk,in,
output reg out
);
always @(posedge clk)begin
out <= in ^ out;
end
endmodule
11.11 Mux and DFF
module top_module
(
input clk,L,r_in,q_in,
output reg Q
);
always@(posedge clk)begin
Q <= L ? r_in : q_in;
end
endmodule
11.12 Mux and DFF
module top_module
(
input clk,w,R,E,L,
output reg Q
);
always@(posedge clk)begin
Q <= (L ? R : (E ? w : Q));
end
endmodule
11.13 DFFs and gates
module top_module
(
input clk,x,
output z
);
wire q0,q1,q2;
dff u1_dff(
.clk(clk),
.d(x ^ q0),
.q(q0)
);
dff u2_dff(
.clk(clk),
.d(x & (~q1)),
.q(q1)
);
dff u3_dff(
.clk(clk),
.d(x | (~q2)),
.q(q2)
);
assign z = ~(q0 | q1 | q2);
endmodule
module dff(
input d,clk,
output reg q
);
always@(posedge clk)
q<=d;
endmodule
11.14 Create circuit from truth table
11.15 Detect an edge
module top_module
(
input clk,
input j,k,
output Q
);
always @(posedge clk)
Q <= j ? (k ? (~Q) : 1) : (k ? 0 : q);
endmodule
11.16 Detect an edges
module top_module
(
input clk,
input [7:0]in,
output reg[7:0]pedge
);
reg [7:0] in1;
always @(posedge clk)begin
in1 <= in;
pedge <= in &(~in1);
end
endmodule
11.17 Edge both edges
module top_module
(
input clk,
input [7:0]in,
output reg[7:0]anyedge
);
reg [7:0] in1;
always @(posedge clk)begin
in1 <= in;
anyedge <= in^in1;
end
endmodule
11.18 Edge capture register
module top_module
(
input clk,reset,
input [31:0]in,
output reg[31:0]out
);
reg [31:0] in1;
always @(posedge clk)begin
in1 <= in;
if(reset)
out <= 32'b0;
else
out <= ((~in)&in1) | out;
end
endmodule
11.19 Dual-edge triggered flip-flop
module top_module
(
input clk,
input d,
output q
);
reg pedge;
reg nedge;
always @(posedge clk)begin
pedge <= d;
end
always @(negedge clk)begin
nedge <= d;
end
assign q = clk ? pedge : nedge;
endmodule