HDLbits答案4

5.Procedure

5.1 Always blocks(combinational)

5.2 Always blocks(clocked)

5.3 If statement

5.4 If statement latches

5.5 Case statement

5.6 Priority encoder

5.7 Priority encoder with casez

5.8 Avoiding latches

6.More Verilog Features

6.1 Conditional ternary operator

6.2 Reduction operators

6.3 Reduction: Even wider gates

6.4 Combinational for-loop: Vector reversal 2

6.5 Combinational for-loop: 255-bit population count

6.6 Generate for-loop: 100-bit binary adder 2

6.7 Generate for-loop: 100-digit BCD adder

5 Procedure

5.1Always blocks(combinational)

module top_module(a,
b,
out_assign,
out_alwaysblock
);
input a,b;
output out_alwaysblock,out_assign;
wire out_assign;
reg out_alwaysblock;
assign out_assign=a&b;

always@(*)
begin
out_alwaysblock<=a&b;
end

endmodule

5.2 Always blocks (clocked)

module top_module(a,
b,
clk,
out_assign,
out_always_comb,
out_always_ff
);
input a,b,clk;
output reg out_always_comb;
output reg out_always_ff;
output wire out_assign;
assign out_assign=a^b;
always@(*)begin
out_always_comb=a^b;
end
always@(posedge clk)begin
out_always_ff<=a^b;
end

endmodule

5.3 If statement

module top_module(a,
b,
sel_b1,
sel_b2,
out_assign,
out_always
);
input a;
input b;
input sel_b1;
input sel_b2;
output wire out_assign;
output reg out_always;

assign out_assign=(sel_b1&sel_b2)?b:a;

always @(*)begin
if(sel_b1&sel_b2)
out_always=b;
else
out_always=a;
end

endmodule

5.4 If statement latches

module top_module(cpu_overheated,
shut_off_computer,
arrived,
gas_tank_empty,
keep_driving
);
input cpu_overheated;
output reg shut_off_computer;
input arrived;
input gas_tank_empty;
output reg keep_driving;

always@(*)begin
  if(cpu_overheated)
    shut_off_computer=1;
  else
	 shut_off_computer=0;
	end
always@(*)begin
 if(~arrived)
    keep_driving=~gas_tank_empty;
  else
    keep_driving=0;
	end 

endmodule

5.5 Case statement

module top_module(sel,
data0,
data1,
data2,
data3,
data4,
data5,
out);
input [2:0]sel;
input [3:0]data0;
input [3:0]data1;
input [3:0]data2;
input [3:0]data3;
input [3:0]data4;
input [3:0]data5;
output reg [3:0]out;
always @(*)begin
case(sel)
3’b000:out=data0;
3’b001:out=data1;
3’b010:out=data2;
3’b011:out=data3;
3’b100:out=data4;
3’b101:out=data5;
default:out=4’b0;
endcase
end

endmodule

5.6 Priority encoder

module top_module(in,
pos
);
input [3:0]in;
output reg[1:0]pos;
always@(*)begin
casez(in)
4’bz1:pos=2’b00;
4’bz10:pos=2’b01;
4’bz100:pos=2’b10;
4’b1000:pos=2’b11;
default:pos=2’b0;
endcase

	end
	endmodule 

5.7 Priority encoder with casez

module top_module(in,
pos
);
input [7:0]in;
output reg[2:0]pos;
always@(*)begin
casez(in)
8’bzzzzzzz1:pos=3’b000;
8’bzzzzzz10:pos=3’b001;
8’bzzzzz100:pos=3’b010;
8’bzzzz1000:pos=3’b011;
8’bzzz10000:pos=3’b100;
8’bzz100000:pos=3’b101;
8’bz1000000:pos=3’b110;
8’b10000000:pos=3’b111;
default:pos=3’b0;
endcase

	end
	endmodule 

5.8 Avoiding latches

module top_module(scancode,
left,
right,
down,
up
);
input [15:0]scancode;
output reg left,right,down,up;

always@(*)begin
left=1’b0;
right=1’b0;
down=1’b0;
up=1’b0;
case(scancode)
16’he06b:left=1’b1;
16’he072:down=1’b1;
16’he074:right=1’b1;
16’he075:up=1’b1;

endcase

	end
	endmodule 

6 More Verilog Features

6.1 Conditional ternary operator

module top_module(a,b,c,d,min);
input [7:0]a,b,c,d;
output [7:0]min;

assign min=((a<b ? a:b)< c ?(a < b ? a : b) : c) < d ?
((a<b ? a:b)< c ?(a < b ? a : b) : c) :d;
endmodule

6.2 Reduction operators

module top_module(in,parity);
input [7:0]in;
output parity;

assign parity=^in;

endmodule 

6.3 Reduction: Even wider gates

module top_module(in,out_and,out_or,out_xor);
input [99:0]in;
output out_and,out_or,out_xor;

assign out_and=∈
assign out_or=|in;
assign out_xor=^in;

endmodule 

6.4 Combinational for-loop: Vector reversal 2

module top_module(in,out);
input [99:0]in;
output [99:0]out;
integer i;
always@(*)
for (i=0;i<=99;i=i+1)
out[i]=in[99-i];
endmodule

6.5 Combinational for-loop: 255-bit population count

module top_module(in,out);
input [254:0]in;
output reg[7:0]out;
integer i;
always @(*)begin
out=8’b0;
for(i=0;i<=254;i=i+1)
out=out+in[i];
end
endmodule

6.6 Generate for-loop: 100-bit binary adder 2

module top_module(a,b,cin,cout,sum);

input [99:0]a;
input [99:0]b;
input cin;

output [99:0]cout;
output [99:0]sum;

generate
genvar i;
for(i=0;i<=99;i=i+1)begin: adder
if(i==0)
assign {cout[0],sum[0]}=a[0]+b[0]+cin;
else
assign{cout[i],sum[i]}=a[i]+b[i]+cout[i-1];
end
endgenerate

endmodule 

6.7 Generate for-loop: 100-digit BCD adder

module top_module(a,b,cin,cout,sum);
input [399:0]a,b;
input cin;
output cout;
output [399:0]sum;

generate
genvar i;
wire [99:0]cout_1;
for(i=0;i<=99;i=i+1)begin:adder
if(i==0)begin
bcd_fadd u_bcd_fadd(
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(cout_1[0])
);
end
else begin
bcd_fadd ui_bcd_fadd(.a(a[4i+3:4i]),
.b(b[4i+3:4i]),
.cin(cout_1[i-1]),
.sum(sum[4i+3:4i]),
.cout(cout_1[i])
);
end
end

assign cout=cout_1[99];
endgenerate

endmodule