HDLbits答案5-Combinational Logic

FPGA终成恶龙

已于 2022-04-05 10:16:26 修改

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分类专栏： HDLbits 文章标签： verilog

于 2022-04-04 19:54:18 首次发布

本文链接：https://blog.csdn.net/weixin_41543509/article/details/123958828

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7.10 Simple circuit A

7.11 Simple circuit B

7.12 Combination circuit A and B

7.13 Ringer or Vibrate?

7.14 Thermostat

7.15 3-bit population count

7.16 Gates and vectors

7.17 Even longer vectors

7Basic Gates

7.1 wire

module top_module(in,out);

   input in;
	output out;
  assign out=in;
	endmodule

7.2 GND

module top_module(out);
	output out;
  assign out=1'b0;
	endmodule

7.3 NOR

module top_module(in1,in2,out);
	input in1,in2;
	output out;
  assign out=~(in1|in2);
	endmodule

7.4 Another gate

module top_module(in1,in2,out);
	input in1,in2;
	output out;
  assign out=in1&(~in2);
	endmodule

7.5 Two gates

module top_module(in1,in2,in3,out);
	input in1,in2,in3;
	output out;
  assign out=~(in1^in2)^in3;
	endmodule

7.6 More logic gates

module top_module(a,b,out_and,out_or,out_xor,out_nand,out_nor,out_xnor,out_anotb);
	input a,b;
	output out_and,out_or,out_xor,out_nand,out_nor,out_xnor,out_anotb;
  assign out_and=a&b;
  assign out_or=a|b;
  assign out_xor=a^b;
  assign out_nand=~(a&b);
  assign out_nor=~(a|b);
  assign out_xnor=a~^b;
  assign out_anotb=a&~b;
  
	endmodule

7.7 7420 chip

module top_module(p1a,
                  p1b,
						p1c,
						p1d,
						p2d,
						p2c,
						p2b,
						p2a,
						p1y,
						p2y
						);
	input wire p1a;
   input wire p1b;
	input wire p1c;
	input wire p1d;
	input wire p2d;
	input wire p2c;
	input wire p2b;
	input wire p2a;
	output p1y;
	output p2y;
   assign p1y=~(p1a&p1b&p1c&p1d);
   assign p2y=~(p2d&p2c&p2a&p2b);
	endmodule

7.8 Truth tables

module top_module(x1,
                  x2,
						x3,
						f
						);
	input x1;
   input x2;
	input x3;
	
   output f;
	
	assign f=(x2&(~x3))|(x1&(~x2)&x3)|(x1&x2&(~x3))|(x1&x2);
   
	endmodule

7.9 Two-bit equality

module top_module(A,
                  B,
						z
					);
	input [1:0]A;
   input [1:0]B;
	
   output z;
	
	assign z=(A==B)?1'b1:1'b0;
   
	endmodule

7.10 Simple circuit A

module top_module(x,
                  y,
						z
					);
	input x;
   input y;
	
   output z;
	
	assign z=(x^y)&x;
   
	endmodule

7.11 Simple circuit B

module top_module(x,
                  y,
						z
					);
	input x;
   input y;
	
   output z;
	
	assign z=x~^y;
   
	endmodule

7.12 Combination circuit A and B

module top_module(x,
                  y,
						z
					);
	input x;
   input y;
	
   output z;
	wire A,B;
	assign A=(x^y)&x;
	assign B=x~^y;
   assign z=(A|B)^(A&B);
	endmodule

7.13 Ringer or Vibrate?

module top_module(ring,
                  vibrate_mode,
						ringer,
						motor
					   );
	input ring;
   input vibrate_mode;
	
   output ringer;
	output motor;

	assign ringer=ring&(~vibrate_mode);
	assign motor=vibrate_mode& ring;
  
	endmodule

7.14 Thermostat

module top_module(too_cold,
                  too_hot,
						mode,
						fan_on,
						heater,
						aircon,
						fan
					   );
	input too_cold;
   input too_hot;
	input mode;
	input fan_on;
	
   output heater;
	output aircon;
	output fan;

	assign heater=mode&too_cold;
	assign aircon=too_hot&(~mode);
	assign fan=fan_on|heater|aircon;
  
	endmodule

7.15 3-bit population count

module top_module(in,
                  out
					   );
	input [2:0]in;
   output wire[1:0]out;
    assign out = in[2]+in[1]+in[0];

	
	
	
	
	
	
	endmodule

7.16 Gates and vectors

module top_module(in,
                  out_both,
						out_any,
						out_different
					   );
        input [3:0]in;
		  output [2:0]out_both;
		  output [3:1]out_any;
		  output [3:0]out_different;
		  
	assign out_both=in[2:0]&in[3:1];
	assign out_any=in[3:1]|in[2:0];
	assign out_different=in^{in[0],in[3:1]};
	
	
	
	
	
	endmodule

7.17 Even longer vectors

	module top_module(in,
                  out_both,
						out_any,
						out_different
					   );
        input [99:0]in;
		  output [98:0]out_both;
		  output [99:1]out_any;
		  output [99:0]out_different;
		  
	assign out_both=in[98:0]&in[99:1];
	assign out_any=in[99:1]|in[98:0];
	assign out_different=in^{in[0],in[99:1]};
	
	
	
	
	
	endmodule