Fsm serialdp-HDLBits

应该算是写的比较简洁的方法了，相比没有奇偶效验的情况没有新增状态。

重点在于1、parity_reset的设置

2、使out_byte不要将奇偶校验位更新进去。

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
        
    reg [3:0] state, next_state;
    parameter idle = 0, start = 1, data = 2, Done = 3, wrong = 4;
    reg [3:0] cnt;
    reg odd;
    reg parity_reset;
    
    parity ins1(clk, parity_reset, in, odd);
    assign parity_reset = (next_state == start) || reset;
    
    always @(*) begin
        case(state)
            idle: next_state = in? idle:start;
            start: next_state = data;
            data: 
            begin
                if (cnt==9 && in && odd)
                    next_state = Done;
                else if (cnt==9 && in && ~odd)
                    next_state = idle;
                else if (cnt == 9 && ~in)
                    next_state = wrong;
                else
                    next_state = data;
            end
            Done: next_state = in? idle:start;
            wrong: next_state = in? idle:wrong;
        endcase
    end
    
    always @(posedge clk) begin
        if (reset) begin
            state <= idle;
            out_byte <= 0;
            // parity_reset <= 1;
        end
        else begin
            case (next_state)
                start: begin
                    cnt <= 0;
                end
                data: begin
                    cnt <= cnt + 1;
                    if (cnt < 8)
                        out_byte <= {in, out_byte[7:1]};
                end
            endcase
            state <= next_state;
        end
    end
    
    assign done = (state == Done);

endmodule