HDLbits Fsm serialdp 问题

直接上代码 (这份是Success的)

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); 
    
    parameter Start = 0, End = 1, Wait = 2, IDLE = 3;
    reg [1:0] state, next_state;
    wire odd_check;
    reg [7:0] count;
    reg [7:0] out;
    
    always @(*) begin
        case (state)
            Norm: next_state = (in)? IDLE: Start;
            Start: begin
                if(count<9) begin
                    next_state = Start;
                    
                end
                else if (count==9) begin
                    if(in)
                    	next_state = End;
                    else
                        next_state = Wait;
                end
                else
                    next_state = IDLE;
            end
            End: next_state = in? IDLE: Start;
            Wait: next_state = in? IDLE: Wait;
            
        endcase
    end
                
    
    # 计数器
    always @(posedge clk) begin
        if (state==Start)begin
            count <= count+1;
            out[count] <= in;
        end

        else begin
            count <= 0; 
            out <= 0;
            
        end
   
    end
            
    wire en;
    assign en = (reset || state == End|| state == IDLE|| state == Wait);
    parity par1(clk,en,in, odd_check);
    
    
    assign done = (state==End && ~odd_check);
    assign out_byte = (state == End && ~odd_check)? out: 0;
    
    always @(posedge clk) begin
        if(reset)
            state<=IDLE;
        else
            state <= next_state;
    end
     
endmodule

问题一

如果我将计数器部分改成如下

 always @(posedge clk) begin
      if (state==Start)begin
          count <= count+1;
      end

      else begin
          count <= 0; 
      end

  end

然后把 out[count] = in加到next_state = Start后面会发现out_byte输出时会少1, 个人猜测跟count有关, 但思来想去不知道到底为什么, 求解答.

问题二

我success的代码里肯定会出现数组溢出的情况, 这在verilog中影响大吗

如有哪位少侠能帮忙解答, 本人不胜感激