HDLBits_Fsm serialdp

相对于上一道题进行了修修改改，一直有10个mismatch，调整了一下状态机，最后终于成功啦。

以下是成功的代码

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //


	parameter IDLE = 4'd0, START = 4'd1, DATA = 4'd2, STOP = 4'd3, WAIT = 4'd4, PARITY = 4'd5;
    reg[2:0] STATE, NEXT_STATE;
    reg[2:0]counter1;
    reg[7:0]out;
    reg par;
    // Use FSM from Fsm_serial
    //FSM PART
    always @ (*)begin
        case(STATE)
            IDLE:NEXT_STATE = in ? IDLE : START;
            START:NEXT_STATE = DATA;
            DATA:NEXT_STATE = (counter1 == 3'd7) ?  PARITY :  DATA;
            PARITY:NEXT_STATE = in ? (par ? STOP : IDLE) : WAIT;
            STOP:NEXT_STATE = in ? IDLE : START;
            WAIT:NEXT_STATE = in ? IDLE : WAIT;
            default:NEXT_STATE = IDLE;
        endcase
    end