module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
);
parameter IDLE = 4'd0;
parameter BIT0 = 4'd1;
parameter BIT1 = 4'd2;
parameter BIT2 = 4'd3;
parameter BIT3 = 4'd4;
parameter BIT4 = 4'd5;
parameter BIT5 = 4'd6;
parameter BIT6 = 4'd7;
parameter BIT7 = 4'd8;
parameter PARI = 4'd9;
parameter STOP = 4'd10;
parameter WAIT = 4'd11;
reg [3:0] state,next_state;
reg done_reg = 1'b0;
reg odd = 1'b0;
reg [8:0] temp_out;
always @(*)
begin
case(state)
IDLE:
begin
if(in) next_state <= IDLE;
else next_state <= BIT0;
end
BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7,PARI:
begin
next_state <= state + 1'b1;
end
STOP:
if(in)
next_state <= IDLE;
else
next_state <= WAIT;
WAIT:
if(in)
next_state <= IDLE;
else
next_state <= WAIT;
default:
next_state <= IDLE;
endcase
end
always @(posedge clk)
begin
if (reset)
begin
state <= IDLE;
end
else
begin
state <= next_state;
end
end
always @(posedge clk)
begin
case(state)
BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7,PARI:
begin
temp_out <= {in,temp_out[8:1]};
done_reg <= 1'b0;
if(in) odd <= ~odd;
end
STOP:
begin
done_reg <= in & odd;
odd <= 1'b0;
end
IDLE,WAIT:
begin
done_reg <= 1'b0;
odd <= 1'b0;
end
default:
begin
done_reg <= 1'b0;
odd <= 1'b0;
end
endcase
end
assign done = done_reg;
assign out_byte = temp_out[7:0];
endmodule