有限状态机之 1001 序列检测器
设计一个“1001”串行数据检测器。
其输入、输出如下所示:
输入 x:000 101 010 010 011 101 001 110 101
输出 z:000 000 000 010 010 000 001 000 000
Verilog源码
//1001序列检测器
module fsm_seq1001(clk,clr,x,z);
input clk,clr,x;
output reg z;
reg [4:0] state;
parameter S0=5'b00001,S1=4'b00010,S2=4'b00100,S3=4'b01000,S4=4'b10000;
always @(posedge clk,posedge clr)
begin
if(clr) state<=S0;
else case(state)
S0: begin
if(x) begin state<=S1; z=1'b0; end
else begin state<=S0; z=1'b0; end
end
S1: begin
if(x) begin state<=S1; z=1'b0; end
else begin state<=S2; z=1'b0; end
end
S2: begin
if(x) begin state<=S1; z=1'b0; end
else begin state<=S3; z=1'b0; end
end
S3: begin
if(x) begin state<=S1; z=1'b1; end
else begin state<=S0; z=1'b0; end
end
default: begin state<=S0; z=1'b0; end
endcase
end
endmodule
testbench
initial
begin
clk=0;clr=1;x=0;
#15 clr=0;
//序列x: 000 101 010 010 011 101 001 110 101
#10 x=0;
#10 x=0;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=0;
#10 x=1;
#10 x=1;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=0;
#10 x=1;
#10 x=1;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=1;
#100 $stop;
$display("Running testbench");
end
always
begin
#5 clk=~clk;
end
endmodule