来一个Verilog代码：异步fifo 及其测试的tb文件

Verilog代码如下：

module async_fifo (
    input clk,
    input rst,
    input wr_en,
    input rd_en,
    input [7:0] wr_data,
    output reg [7:0] rd_data,
    output full,
    output empty
);
    parameter depth = 8;
    reg [7:0] mem [0:depth-1];
    reg [3:0] wr_ptr, rd_ptr;

    always @ (posedge clk) begin
        if (rst) begin
            wr_ptr <= 0;
            rd_ptr <= 0;
        end else begin
            if (wr_en &amp; ~full) begin
                mem[wr_ptr] <= wr_data;
                wr_ptr <= wr_ptr + 1;
            end
            if (rd_en &amp; ~empty) begin
                rd_data <= mem[rd_ptr];
                rd_ptr <= rd_ptr + 1;
            end
        end
    end

    assign full = (wr_ptr == rd_ptr + depth);
    assign empty = (wr_ptr == rd_ptr);

endmodule