HDLbits代码答案（3.1 Combinational Logic）持更

3.Circuits

3.1Combinational Logic

3.1.1Basic Gates

• Wire

module top_module (
    input in,
    output out);

    assign out = in;
    
endmodule

• GND

module top_module (
    output out);

    assign out = 1'b0;
    
endmodule

• NOR

module top_module (
    input in1,
    input in2,
    output out);

    assign out =~(in1 | in2);
    
endmodule

• Another gate

module top_module (
    input in1,
    input in2,
    output out);

    assign out = in1 & (~in2);
    
endmodule

• Two gates

module top_module (
    input in1,
    input in2,
    input in3,
    output out);

    assign out = in3 ^ ~(in1^in2);
    
endmodule

• More logic gates

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
    assign out_and = a & b;
    assign out_or = a | b;
    assign out_xor = a ^ b;
    assign out_nand = ~ (a & b); 
    assign out_nor = ~ (a | b);
    assign out_xnor = ~ (a ^ b);
    assign out_anotb = a & ~b;

endmodule

• 7420 chip

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );

    assign p2y = ~(p2a & p2b & p2c & p2d);
    assign p1y = ~(p1a & p1b & p1c & p1d);

endmodule

• Truth tables
  

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);

    wire [2:0]mid;
    assign mid = {x3,x2,x1};
    
    always@(*)
        begin
            case(mid) 
                3'b000,3'b001,3'b100,3'b110: f = 0;
                3'b010,3'b011,3'b101,3'b111: f = 1;
                default:;
            endcase
        end
    
endmodule

• Two-bit equality

module top_module ( input [1:0] A, input [1:0] B, output z ); 

    assign z = (A == B)?1:0;
    
endmodule

• Simple circuit A

module top_module (input x, input y, output z);

    assign z