HDLBits答案合集（一）

本文为本人HDL刷题代码，如有问题请及时联系

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前言

本文为HDL刷题代码（一），相关文章会在博客陆续发出

相关文章：
HDLBit 整理1
HDLBit 整理2
HDLBit 整理3
HDLBits 答案合集（一）

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提示：以下是本篇文章正文内容，下面案例可供参考

一、Getting Started

2个基础练习

1.1 Step one

module top_module( output one );

    assign one = 1;

endmodule

1.2 Zero

module top_module(zero);
    output zero;
    assign zero = 1'b0;

endmodule

---

二、Verilog language

2.1 Basics

共有8个练习

2.1.1 wire

module top_module( input in, output out );
    assign out = in;

endmodule

2.1.2 Wire4

module top_module( 
    input a,b,c,
    output w,x,y,z );
    assign w = a;
    assign x = b;
	assign y = b;
    assign z = c;
endmodule

2.1.3 Notgate

module top_module( input in, output out );
    assign out = ~in;

endmodule

2.1.4 Andgate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = a&b;

endmodule

2.1.5 Norgate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = ~(a|b);

endmodule

2.1.6 Xnorgate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = a?(b?1:0):(b?0:1);
endmodule

2.1.7 Wire decl

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    
    wire w1,w2,w3;
    
    assign out_n = ~w1;
    assign out = w1;
    assign w1 = w2|w3;
    assign w2 = a&b;
    assign w3 = c&d;
 
endmodule

2.1.8 7458

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    assign p1y = (p1a & p1b & p1c)|(p1d & p1e & p1f);
    assign p2y = (p2a & p2b)|(p2c & p2d);

endmodule

---

2.2 vectors

共有9个练习

2.2.1 vector0

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); // Module body starts after module declaration
    
    assign outv = vec;
    assign o0 = vec[0];
    assign o1 = vec[1];
    assign o2 = vec[2];

endmodule

2.2.2 Vector1

module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo );
    
    assign out_lo[7:0] = in[7:0];
    assign out_hi[7:0] = in[15:8];
    
endmodule

2.2.3 Vector2

module top_module( 
    input [31:0] in,
    output [31:0] out );//

    // assign out[31:24] = ...;
    assign out[7:0] = in[31:24];
    assign out[15:8] = in[23:16];
    assign out[23:16] = in[15:8];
    assign out[31:24] = in[7:0];

endmodule

2.2.4 Vectorgates

module top_module(
	input [2:0] a, 
	input [2:0] b, 
	output [2:0] out_or_bitwise,
	output out_or_logical,
	output [5:0] out_not
);
	
	assign out_or_bitwise = a | b;
	assign out_or_logical = a || b;

	assign out_not[2:0] = ~a;	// Part-select on left side is o.
	assign out_not[5:3] = ~b;	//Assigning to [5:3] does not conflict with [2:0]
	
endmodule

2.2.5 Gates4

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);
    assign out_and = in[3] & in[2] & in[1] & in[0];  
    assign out_or = in[3] | in[2] | in[1] | in[0];
    assign out_xor = in[3] ^ in[2] ^ in[1] ^ in[0];
    
/*简写形式
    assign out_and = & in;
    assign out_or = | in;
    assign out_xor = ^ in;
*/
endmodule

2.2.6 Vector3

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );//
    
    assign {w,x,y,z} = {a,b,c,d,e,f,2'b11};

endmodule

2.2.7 Vectorr

module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;
  
endmodule

2.2.8 Vectorr

module top_module (
    input [7:0] in,
    output [31:0] out );
    
    assign out = {{24{in[7]}},in};
endmodule

2.2.9 Vector5

module top_module (
    input a, b, c, d, e,
    output [24:0] out );
    
    assign out = ~({{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}}) ^ ({5{a,b,c,d,e}});

endmodule

---

2.3 modules：hierachy

共有9个练习

2.3.1 module

module top_module ( input a, input b, output out );
    mod_a	U1(
        .in1(a),
        .in2(b),
        .out(out)
    );
endmodule

2.3.2 module pos

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a u1(out1, out2,a,b,c,d);  //题目未给出mod_a端口名称，且按照顺序连接
endmodule

2.3.3 module name

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a u1(
        .in1(a),
        .in2(b),
        .in3(c),
        .in4(d),
        .out1(out1),
        .out2(out2)
    );
endmodule

2.3.4 Module shift

module top_module ( input clk, input d, output q );
    wire q1,q2;
    
    // 定义两个wire用于连接
    my_dff u1(.q(q),.clk(clk),.d(q1));
    my_dff u2(.q(q1),.clk(clk),.d(q2));
    my_dff u3(.q(q2),.clk(clk),.d(d));

endmodule

2.3.5 Module shift8

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    wire [7:0] q0,q1,q2;
    
    my_dff8 u1(.q(q0),.d(q1),.clk(clk));
    my_dff8 u2(.q(q1),.d(q2),.clk(clk));
    my_dff8 u3(.q(q2),.d(d),.clk(clk));
    
    always @(posedge sel or posedge clk )
        begin
        	case(sel)
            	2'b00:	q <= d;   // 时序电路用非阻塞赋值
            	2'b01:	q <= q2;
            	2'b10:	q <= q1;
            	2'b11:	q <= q0;
        	endcase
        end
endmodule

2.3.6 Module add

// 不需要去处理add16内部的加法，只需将模块连接起来即可
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    
    wire  [15:0] a1,a2,b1,b2,s1,s2;
    wire c1,c2;
    assign c1 = 0;
    assign a1 = a[15:0];    // 可以直接将a[15:0]在模块中实例化，如 .a(a[15:0])
    assign a2 = a[31:16];
    assign b1 = b[15:0];
    assign b2 = b[31:16];
    
    add16 u1(.sum(s1),.a(a1),.b(b1),.cin(c1),.cout(c2));
    add16 u2(.sum(s2),.a(a2),.b(b2),.cin(c2));
    
    assign sum = {s2,s1};
    
endmodule

2.3.7 Module fadd

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);//
    wire C1,C2;
    assign C1 = 0;
    add16 U1(.a(a[15:0]),.b(b[15:0]),.cin(C1),.cout(C2),.sum(sum[15:0]));
    add16 U2(.a(a[31:16]),.b(b[31:16]),.cin(C2),.sum(sum[31:16]));

endmodule

module add1 ( input a, input b, input cin,   output sum, output cout );

	assign sum = a^b^cin;      // 全加器的逻辑表达式
    assign cout = (a&b) | (a&cin) | (b&cin);
	// 另一种写法     assign {cout,sum} = a+b+cin;
endmodule

2.3.8 Module cseladd

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire c1,c2,c3,ct1;
    wire [15:0] s0,s1;
    
    assign c1 = 0;
    assign c2 = 0;
    assign c3 = 1;
    
    add16 u1(.a(a[15:0]),.b(b[15:0]),.cin(c1),.cout(ct1),.sum(sum[15:0]));
    add16 u2(.a(a[31:16]),.b(b[31:16]),.cin(c2),.sum(s0));
    add16 u3(.a(a[31:16]),.b(b[31:16]),.cin(c3),.sum(s1));
    
    always @(*) begin
        if(ct1)	sum[31:16] = s1;
        else	sum[31:16] = s0;
    end
    
endmodule

2.3.9 Module addsub

module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    wire [31:0] b1;
    wire c1;
    assign b1 = b ^ {32{sub}};
    
    add16 u1(.a(a[15:0]),.b(b1[15:0]),.cin(sub),.cout(c1),.sum(sum[15:0]));
    add16 u2(.a(a[31:16]),.b(b1[31:16]),.cin(c1),.sum(sum[31:16]));

endmodule

---

2.4 procedures

共有8个练习

2.4.1 Alwaysblock1

module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
    assign out_assign = a&b;
    always @(*)
        out_alwaysblock = a&b;

endmodule

2.4.2 Alwaysblock2

module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
    
    assign out_assign = a^b;
    always @(*)
        out_always_comb = a^b;
    always @(posedge clk)
        out_always_ff <= a^b;    // 组合电路用阻塞赋值，时序用非阻塞赋值

endmodule

2.4.3 always if

module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
    
    assign out_assign = (sel_b1 & sel_b2) ? b:a;
    always @(*) begin
        if(sel_b1 & sel_b2) out_always = b;
        else out_always = a;
    end
endmodule

2.4.4 always if2

module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
            shut_off_computer = 1;
        else
            shut_off_computer = 0;
    end
    
    always @(*) begin
        if (arrived | gas_tank_empty)
            keep_driving = 0;
        else
            keep_driving = 1;
    end
endmodule

2.4.5 Always case

module top_module ( 
    input [2:0] sel, 
    input [3:0] data0,
    input [3:0] data1,
    input [3:0] data2,
    input [3:0] data3,
    input [3:0] data4,
    input [3:0] data5,
    output reg [3:0] out   );//

    always@(*) begin  // This is a combinational circuit
        case(sel)
            3'b000: out = data0;
            3'b001: out = data1;
            3'b010: out = data2;
            3'b011: out = data3;
            3'b100: out = data4;
            3'b101: out = data5;
            default: out = 0;
        endcase
    end
endmodule

2.4.6 Always case2

module top_module (
    input [3:0] in,
    output reg [1:0] pos  );
    always @(*) begin
        case(in)
            4'b0000: pos = 0;
            4'b0001: pos = 0;
            4'b0010: pos = 1;
            4'b0011: pos = 0;
            4'b0100: pos = 2;
            4'b0101: pos = 0;
            4'b0110: pos = 1;
            4'b0111: pos = 0;
            4'b1000: pos = 3;
            4'b1001: pos = 0;
            4'b1010: pos = 1;
            4'b1011: pos = 0;
            4'b1100: pos = 2;
            4'b1101: pos = 0;
            4'b1110: pos = 1;
            4'b1111: pos = 0;
    		default: pos = 0;
        endcase
    end
endmodule

2.4.7 Always casez

module top_module (
    input [7:0] in,
    output reg [2:0] pos  );
    always @(*)
        casez(in)
            8'bzzzzzzz1: pos = 0;
            8'bzzzzzz1z: pos = 1;
            8'bzzzzz1zz: pos = 2;
            8'bzzzz1zzz: pos = 3;
            8'bzzz1zzzz: pos = 4;
            8'bzz1zzzzz: pos = 5;
            8'bz1zzzzzz: pos = 6;
            8'b1zzzzzzz: pos = 7;
            default: pos = 0;
        endcase
endmodule

2.4.8 Always nolatches

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    
    always @(*) begin
        left = 0; right = 0; up = 0; down = 0;
    	case(scancode)
        	16'he06b: left = 1;
            16'he072: down = 1;
            16'he074: right = 1;
            16'he075: up = 1;
        endcase
    end
endmodule

2.5 more Verilog features

共有7个练习

2.5.1 conditional

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//
    
    assign min = (a<b) ? 
        ((a<c) ? ((a<d) ? a:d) : ((c<d)? c:d)):
        ((b<c) ? ((b<d) ? b:d) : ((c<d)?c:d));

endmodule

2.5.2 reduction

module top_module (
    input [7:0] in,
    output parity); 
   
    assign parity = ^ in[7:0];  // 偶检验需使1的数量为偶数
endmodule

2.5.3 gate100

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
    assign out_and = & in[99:0];
    assign out_or  = | in[99:0];
    assign out_xor = ^ in[99:0];

endmodule

2.5.4 vector100r

module top_module( 
    input [99:0] in,
    output reg [99:0] out
);
	// for语句会占用大量资源，因此采用generate for语句
    genvar i;
    generate    
        for(i=0;i<100;i=i+1)begin:reverse_bit  
            assign out[99-i] = in[i];
        end
    endgenerate
endmodule

2.5.5 popcount255

module top_module( 
    input [254:0] in,
    output reg [7:0] out );
    
    integer i;
    always @(*) begin
        out = 0;
        for(i=0;i<$bits(in);i=i+1) begin    // $bits（）为计算位宽函数
            if(in[i]) out = out+8'b1;  
        end
    end
endmodule

2.5.6 adder 100i

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    
    assign sum[0] = cin^ a[0] ^ b[0];
    assign cout[0] = (a[0]&b[0]) | (a[0]&cin) | (b[0]&cin);
    
    genvar i;
    generate
        for(i=1;i<100;i=i+1)begin: adder
            assign sum[i] = cout[i-1]^a[i]^b[i];
            assign cout[i] = (a[i]&b[i]) | (a[i]&cout[i-1]) | (b[i]&cout[i-1]);
        end
    endgenerate
endmodule

2.5.7 bcdadd100

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    
    assign sum[0] = cin^ a[0] ^ b[0];
    assign cout[0] = (a[0]&b[0]) | (a[0]&cin) | (b[0]&cin);
    
    genvar i;
    generate
        for(i=1;i<100;i=i+1)begin: adder
            assign sum[i] = cout[i-1]^a[i]^b[i];
            assign cout[i] = (a[i]&b[i]) | (a[i]&cout[i-1]) | (b[i]&cout[i-1]);
        end
    endgenerate
endmodule