Verilog - 利用加法器实现乘法器 [代码]

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	module multiplier
		(
		input [2:0] x,
		input [2:0] y,
		output [5:0] mult_out
		);
		
		wire [2:0] temp0 = y[0] ? x : 3'd0;
		wire [2:0] temp1 = y[1] ? x : 3'd0;
		wire [2:0] temp2 = y[2] ? x : 3'd0;
		
		assign mult_out = temp0 + (temp1 << 1) + (temp2 << 2);

	endmodule