计算机组成原理实验之一：32位ALU的设计

Verilog HDL 实现简单的32位ALU算术逻辑运算器

接触到EDA软件也有差不多七八个月了，如今学了计算机组成原理，正巧有计组的实验，于是就打算写个系列的博客。
转载需注明出处！

直接上代码

module alu_32_top(
    input clkin,
    input [2:0]sel,
    output [7:0] scan,
    output [7:0] seg7
    );
    
    wire [31:0] data_temp;
    alu_32 u0(.sel(sel),.y(data_temp));
     led_seg7 u1(.clkin(clkin),.datain(data_temp),.scan(scan),.seg7(seg7));  
endmodule

module alu_32(sel,y);
    input [2:0] sel;
    output [31:0] y;
    
    reg[31:0] y;
    reg [31:0] dataA = 32'h00ffbb11, dataB = 32'h0000fffa;
    always@(sel)begin
       if(sel==3'b000) y = dataA + dataB; 
       else if(sel==3'b001) y = dataA - dataB;
       else if(sel==3'b010) y = dataA * dataB;
       else if(sel==3'b011) y = dataA / dataB;
       else if(sel==3'b100) y = dataA & dataB;
       else if(sel==3'b101) y = dataA | dataB;
       else y =8'b0;
       //此处可以自己添加其他的逻辑计算，例如移位等等
     end    
endmodule

module led_seg7(
input clkin,
input [31:0] datain,
output [7:0] scan,
output [7:0] seg7
    );
    
 reg [7:0] scan;
 reg [7:0] seg7=0;
 reg [2:0] cnt1=0;
 reg [3:0] data_temp;
 reg clkout=0;
 
 reg[31:0] cnt=0;
 reg clk_temp=0;
 
 //50MHZ,20ns,500000*20ns=100ms
 always @(posedge clkin) begin
     case(cnt)
         32'd50000: begin            
             clk_temp <= ~clk_temp;
             cnt <= 0;
             end             
         default: begin
             cnt <= cnt + 1;
             end
     endcase
     clkout <= clk_temp;
 end
    
 always @(posedge clkout)
   begin
       // if(~reset) 
      //      begin
      //          cnt1 = 3'b000;
      //         scan = 8'b11111111;              
     //       end
       
             if(cnt1 == 3'b111) 
                cnt1 = 3'b000;                
             else
                cnt1 = cnt1 + 1 ;     
            //end
   end
   
   always @(cnt1)
   begin     
       case(cnt1)
            3'b000 : begin scan <= 8'b11111110; data_temp <= datain[3:0];    end   
            3'b001 : begin scan <= 8'b11111101; data_temp <= datain[7:4];    end  
            3'b010 : begin scan <= 8'b11111011; data_temp <= datain[11:8];   end      
            3'b011 : begin scan <= 8'b11110111; data_temp <= datain[15:12];  end
            3'b100 : begin scan <= 8'b11101111; data_temp <= datain[19:16];  end      
            3'b101 : begin scan <= 8'b11011111; data_temp <= datain[23:20];  end   
            3'b110 : begin scan <= 8'b10111111; data_temp <= datain[27:24];  end      
            3'b111 : begin scan <= 8'b01111111; data_temp <= datain[31:28];  end   
            default: begin scan <= 8'b11111111; data_temp <= 32'd0;  end
        endcase    
       
        case(data_temp)
                  4'b0000 : seg7 <= 8'b00111111;    
                  4'b0001 : seg7 <= 8'b00000110;  
                  4'b0010 : seg7 <= 8'b01011011;        
                  4'b0011 : seg7 <= 8'b01001111;
                  4'b0100 : seg7 <= 8'b01100110;
                  4'b0101 : seg7 <= 8'b01101101;
                  4'b0110 : seg7 <= 8'b01111101;
                  4'b0111 : seg7 <= 8'b00000111;
                  4'b1000 : seg7 <= 8'b01111111;
                  4'b1001 : seg7 <= 8'b01101111;
                  4'b1010 : seg7 <= 8'b01110111;
                  4'b1011 : seg7 <= 8'b01111100;
                  4'b1100 : seg7 <= 8'b00111001;
                  4'b1101 : seg7 <= 8'b01011110;   
                  4'b1110 : seg7 <= 8'b01111001;
                  4'b1111 : seg7 <= 8'b01110001;                                         
                  default : seg7 <= 8'b00000000;
        endcase
 end
endmodule

这是文件的组织结构，保存后会自动形成这样的一个结构

本实验采用的开发板是：xc7a200tfbg676-2
约束文件内容如下：

set_property PACKAGE_PIN D3 [get_ports {scan[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {scan[7]}]
set_property PACKAGE_PIN D25 [get_ports {scan[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {scan[6]}]
set_property PACKAGE_PIN D26 [get_ports {scan[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {scan[5]}]
set_property PACKAGE_PIN E25 [get_ports {scan[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {scan[4]}]
set_property PACKAGE_PIN E26 [get_ports {scan[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {scan[3]}]
set_property PACKAGE_PIN G25 [get_ports {scan[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {scan[2]}]
set_property PACKAGE_PIN G26 [get_ports {scan[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {scan[1]}]
set_property PACKAGE_PIN H26 [get_ports {scan[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {scan[0]}]
set_property PACKAGE_PIN C4 [get_ports {seg7[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg7[7]}]
set_property PACKAGE_PIN C3 [get_ports {seg7[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg7[6]}]
set_property PACKAGE_PIN E6 [get_ports {seg7[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg7[5]}]
set_property PACKAGE_PIN B2 [get_ports {seg7[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg7[4]}]
set_property PACKAGE_PIN B4 [get_ports {seg7[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg7[3]}]
set_property PACKAGE_PIN E5 [get_ports {seg7[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg7[2]}]
set_property PACKAGE_PIN D4 [get_ports {seg7[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg7[1]}]
set_property PACKAGE_PIN A2 [get_ports {seg7[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg7[0]}]
set_property PACKAGE_PIN AC21 [get_ports {sel[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[2]}]
set_property PACKAGE_PIN AD24 [get_ports {sel[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[1]}]
set_property PACKAGE_PIN AC22 [get_ports {sel[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[0]}]
set_property PACKAGE_PIN AC19 [get_ports clkin]
set_property IOSTANDARD LVCMOS33 [get_ports clkin]

之后的上实验板验证就不再过多的赘述了