Zynq Mipi PCIe通路搭建

前言

通路搭建

整体非常简单，MIPI+PCIE+ZYNQ
MIPI部分

编译时：
demosic无法编译问题：

https://www.xilinx.com/support/answers/70400.html
主要是下面这句

compile_c [get_ips design_1_v_tpg_0]

或者全部自动检测

foreach ip_in_proj [get_ips] {compile_c [get_ips $ip_in_proj]}

Petalinux环境搭建

netstat

sudo apt install net-tools

zlib1g：i386安装

sudo dpkg --add-architecture i386
sudo apt-get update
sudo apt-get install zlib1g:i386

DPHY选择

总结下：
（1）CK必须是DBC 、GBC、DBC_GC
（2）最好连续，在一个bank内

约束实例

驱动使用

参考黑金pipeline

设备树

&i2c0 {
	ov5640: camera@3c {
		compatible = "ovti,ov5640";
		reg = <0x3c>;
		clocks = <&misc_clk_a>;
		clock-names = "xclk";
		/* rotation = <180>; */
		DOVDD-supply = <&cam_reg_1v8>;
		AVDD-supply = <&cam_reg_2v8>;
		DVDD-supply = <&cam_reg_1v5>;
		port {
			/* MIPI CSI-2 bus endpoint */
			ov5640_to_mipi_csi2: endpoint {
				remote-endpoint = <&csiss_in>;
				clock-lanes = <0>;
				data-lanes = <1 2>;
			};
		};
	};
};


&mipi_csi2_rx_subsyst_0{
	compatible = "xlnx,mipi-csi2-rx-subsystem-2.0";
	csiss_ports: ports {
		#address-cells = <1>;
		#size-cells = <0>;
		csiss_port0: port@0 {
			reg = <0>;

			xlnx,video-format = <0>;
			xlnx,video-width = <8>;

			csiss_out: endpoint {
				remote-endpoint = <&csc_in>;
			};
		};
		csiss_port1: port@1 {
			reg = <1>;

			xlnx,video-format = <0>;
			xlnx,video-width = <8>;

			csiss_in: endpoint {
				data-lanes = <1 2>;
				remote-endpoint = <&ov5640_to_mipi_csi2>;
			};
		};
	};
};

&v_proc_ss_0{
	compatible = "xlnx,v-vpss-csc";
	reset-gpios = <&gpio 86 1>;
	csc_ports: ports {
		#address-cells = <1>;
		#size-cells = <0>;
		csc_port0: port@0 {
			reg = <0>;
			xlnx,video-format = <3>;
			xlnx,video-width = <8>;
			csc_in: endpoint {
				remote-endpoint = <&csiss_out>;
			};
		};
		csc_port1: port@1 {
			reg = <1>;
			xlnx,video-format = <3>;
			xlnx,video-width = <8>;
			csc_out: endpoint {
				remote-endpoint = <&vcap_in>;
			};
		};
	};
};


&v_frmbuf_wr_0 {
	compatible = "xlnx,axi-frmbuf-wr-v2.1";
	reset-gpios = <&gpio 85 1>;
};

&amba_pl {
	vcap_mipi {
		compatible = "xlnx,video";
		dma-names = "port0";
		dmas = <&v_frmbuf_wr_0 0>;
		vcap_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
			vcap_port: port@0 {
				direction = "input";
				reg = <0>;
				vcap_in: endpoint {
					remote-endpoint = <&csc_out>;
				};
			};
		};
	};
};