序列检测器方法和技巧

实现：
方法1、状态机，
方法2、移位寄存器，移位作比较即可
方法1：

module Sequence_detection(
input logic clk,
input logic rstn,
input logic bit_in,
output logic detected
    );

parameter S0=4'b0000,
S1=4'b0001,
S2=4'b0010,
S3=4'b0011,
S4=4'b0100,
S5=4'b0101;
//
reg [3:0] cur_state,next_state;
always@(posedge clk,negedge rstn)
if(!rstn)
    cur_state<=S0;
else 
    cur_state<=next_state;
//
always@(*)
begin
    case(cur_state)
        S0:if(bit_in)
               next_state=S1;
           else
               next_state=S0;
        S1:if(bit_in)
               next_state=S1;
           else
               next_state=S2;           //10
        S2:if(bit_in)
               next_state=S1;
            else
               next_state=S3;           //100
        S3:if(bit_in)
               next_state=S4;            //1001
            else
               next_state=S0;
        S4:if(bit_in)
                next_state=S1;
            else
                next_state=S5;           //10010
        S5:if(bit_in)
                next_state=S1;
            else
                next_state=S0;
        default:next_state=S0;
    endcase
end
//
assign detected=(cur_state==S5)?1'b1:1'b0;
endmodule

方法2：

module top(
input clk,
input rstn,
input bit_in,
input valid,
output detected
);
reg [4:0] shift_reg;
reg [31:0] count;

always@(posedge clk, negedge rstn) begin
	if(!rstn)
		shift_reg<='b0;
	else if(valid) begin
		shift_reg<={shift_reg[3:0],bit_in};
	end
end
always@(posedge clk,negedge rstn) begin
	if(!rstn) begin
		count<='b0;
	end
	else if(detected)
		count<='b0;
	else if(valid)
		count<=count+1'b1;
end
assign detected=(5'b00111==shift_reg && count>=32'd4)?1'b1:1'b0;
endmodule