【unity报错】NullReferenceException: Object reference not set to an instance of an object

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NullReferenceException: Object reference not set to an instance of an object

NullReferenceException

“你调用的对象是空的。” 为那些在初学者 C#/.NET 程序员时从未遇到过此错误消息的人投下第一块石头。

当您收到 NullReferenceException 时,就会出现这个臭名昭著且可怕的错误消息。当您尝试访问当前持有空引用的变量的成员(例如,方法或属性)时,会抛出此异常。

但是什么是空引用呢?首先什么是“参考”?如何阻止 NullReferenceException 在您的代码中发生?这就是我们今天要介绍的内容。

我们将从基础开始,简要说明 C#/.NET 中的引用。之后,您将了解什么是空引用。在这一点上,您已经看到了整个画面的一半。

在这一轮理论定义之后,我们将进入更实际的问题,教你如何在实践中避免 NullReferenceException。让我们深入挖掘。

什么是空引用

我们已经知道 NullReferenceException 是由空引用引起的。但是什么是空引用呢?它与非空引用有何不同?

在 .NET 中,您可以将数据类型分为两类:值类型和引用类型。如果你有一个值类型的变量,它存储值本身。另一方面,引用类型变量本身不保存值。它们持有指向对象在内存中所在位置的引用。

如果它能帮助您更好地形象化它,您可以将引用视为指向网页的链接,或指向计算机上文件的快捷方式。诸如 int(和其他数字原始类型)、DateTime 和 boolean 之类的类型是值类型。也就是说,结构是值类型。类是引用类型。

因此,引用是引用类型的变量包含的内容。不过,这些变量可以指向“无”,这就是我们所说的空引用:不指向任何对象的引用。当您尝试调用上述变量的方法或另一个成员时,您会得到 NullReferenceException。

如何避免

空引用错误占所有应用程序错误的很大一部分。它们通常是由于没有添加额外的逻辑来确保对象在使用它们之前具有有效值而导致的非常简单的问题。下面是一些避免 NullReferenceException 的方法。

如果传入的变量“text”为空,以下代码将抛出 NullReferenceException。您不能对空字符串调用 ToUpper()。

public void MyMethod(string text)

{

  //Throws exception if text == null

  if (text.ToUpper() == “Hello World”)

  {

       //do something

  }

}

使用 Null 条件运算符来避免 NullReferenceExceptions
您可以使用“?”来代替大量的“variable != null”类型检查。并且您的代码将短路并返回 null 而不是抛出异常。通过下面的一些示例,这将更有意义:

text?.ToUpper(); //前面的例子,将返回空

int? length = customerList?.Length; // 如果 customerList 为 null,则为 null   

Customer first = customerList?[0];  // 如果 customerList 为 null,则为 null 

int? count = customerList?[0]?.Orders?.Count();  //如果 customerList、第一个客户或订单为 null,则为 null

使用 Null 合并来避免 NullReferenceExceptions
另一个很棒的功能是null coalescing,即“??” 操作符。它非常适合为空变量提供默认值。它适用于所有可为空的数据类型。

以下代码在没有空合并的情况下抛出异常。添加“?? new List()”防止“对象引用未设置到对象的实例”异常。

List<string> values = null;
foreach (var value in values ?? new List<string>())
{
    Console.WriteLine(value);
} 

空值导致问题的简单示例

一些最常见的原因是设置、数据库调用或未返回预期值的 API 类型调用。例如,您向数据库中添加了一个新字段,但没有为每条记录填充默认值。随机记录被查询,并且代码没有说明新字段为空。

编程的黄金法则

多年来,我一直对我的团队说一句话。我称之为编程的黄金法则。我认为每个新程序员都需要一个能说明这一点的纹身。

“如果它可以为空,它将为空”

好消息是,通过添加额外的逻辑和代码来确保对象在尝试使用它们之前不为空,可以避免很多空引用错误。开发人员应该始终假设一切都是无效的,并且在他们的代码中非常防御。假设每个数据库调用都会失败,每个字段都会弄乱其中的数据。良好的异常处理最佳实践至关重要。
防止空引用异常的技巧

  1. 用有效值初始化变量。

2.如果变量可以为null,则检查是否为null并适当处理

3.使用“?” 可能时在方法上使用运算符。stringvar?.ToUpper();

4.使用像Resharper这样的工具来帮助指出潜在的空引用异常
使用 C# 8.0 的可空类型避免 NullReferenceException
空引用错误的主要原因之一是在 C 中,每个引用类型对象始终可以为空。如果您,开发人员,有权说:“我希望这个字符串永远不会为空”怎么办?更好的是,如果这个决定是由编译器本身强制执行的,以防止您和其他开发人员意外地将 null 分配给所述变量怎么办?听起来不错?好消息:这是 C# 第八版的一个真正的特性,毫不奇怪,它被称为可空类型。
该功能以巧妙而强大的方式工作。它将引用类型重新定义为默认情况下不可为 null——许多人认为它们从一开始就应该如此。然后,它添加了一种新的语法,允许您定义可为空的变量(不过,这并不是真正的新语法,因为它与多年来用于可空值类型的语法相同。)

为了更好地理解,请看以下示例:

static int Add(string numbers)
{
return numbers.Split(“,”).Select(int.Parse).Sum();
}

在 8.0 之前的 C# 版本中,上面的代码是危险的。numbers 变量可能为 null,这会在尝试使用 Split 方法时导致 NullReferenceException。

使用 C# 8.0 可为空的引用类型功能,你会很安全。该变量永远不会为 null,对 Split 方法的调用也永远不会抛出异常。任何将 null 传递给 Add 方法的尝试都会导致编译错误。

但是如果你想在数字中允许 null 怎么办?在这种情况下,您只需在类型名称后添加一个问号:

static int Add(string? numbers)
{
return numbers.Split(“,”).Select(int.Parse).Sum();
}

现在情况发生了巨大变化。由于数字现在可以为空,编译器会提示您检查变量的值,并发出警告(您可以将警告变成编译器错误,以提高安全性):
在这里插入图片描述
编译器让我知道“数字”可以为空。可能的解决方案包括:

使用 if 语句确保变量具有有效引用
在调用 Split 方法时使用已经提到的空合并运算符
通过删除问号再次使“numbers”变量不可为空
抑制给我们警告的规则(这会破坏整个目的,但是嘿,这是一个选择。)
请记住,此功能是可选的。也就是说,默认情况下它是禁用的,您必须在项目配置中激活它。这样做的原因是运送已经启用的功能会导致大多数代码库发生重大变化。
所以:遵循我的黄金法则:如果它可以为空,它将为空!

其他原因

unity3d函数执行顺序:Awake->OnEable->Start->FixedUpdate->Update->LateUpdate->OnGUI->Reset->OnDisable->OnDestroy
注意是不是在调用时,变量还没有初始化

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Table of Contents Section 1 Introduction to SystemVerilog ...................................................................................................... 1 Section 2 Literal Values.................................................................................................................................. 4 2.1 Introduction (informative) ...............................................................................................................4 2.2 Literal value syntax..........................................................................................................................4 2.3 Integer and logic literals ..................................................................................................................4 2.4 Real literals ......................................................................................................................................5 2.5 Time literals .....................................................................................................................................5 2.6 String literals....................................................................................................................................5 2.7 Array literals ....................................................................................................................................6 2.8 Structure literals ...............................................................................................................................6 Section 3 Data Types....................................................................................................................................... 8 3.1 Introduction (informative) ...............................................................................................................8 3.2 Data type syntax...............................................................................................................................9 3.3 Integer data types ...........................................................................................................................10 3.4 Real and shortreal data types .........................................................................................................11 3.5 Void data type ................................................................................................................................11 3.6 chandle data type ...........................................................................................................................11 3.7 String data type ..............................................................................................................................12 3.8 Event data type...............................................................................................................................16 3.9 User-defined types .........................................................................................................................16 3.10 Enumerations .................................................................................................................................17 3.11 Structures and unions.....................................................................................................................22 3.12 Class...............................................................................................................................................26 3.13 Singular and aggregate types .........................................................................................................27 3.14 Casting ...........................................................................................................................................27 3.15 $cast dynamic casting ....................................................................................................................28 3.16 Bit-stream casting ..........................................................................................................................29 Section 4 Arrays ............................................................................................................................................ 32 4.1 Introduction (informative) .............................................................................................................32 4.2 Packed and unpacked arrays ..........................................................................................................32 4.3 Multiple dimensions ......................................................................................................................33 4.4 Indexing and slicing of arrays........................................................................................................34 4.5 Array querying functions ...............................................................................................................35 4.6 Dynamic arrays ..............................................................................................................................35 4.7 Array assignment ...........................................................................................................................37 4.8 Arrays as arguments.......................................................................................................................38 4.9 Associative arrays ..........................................................................................................................39 4.10 Associative array methods .............................................................................................................41 4.11 Associative array assignment.........................................................................................................44 4.12 Associative array arguments ..........................................................................................................44 4.13 Associative array literals................................................................................................................44 4.14 Queues ...........................................................................................................................................45 4.15 Array manipulation methods .........................................................................................................47 Section 5 Data Declarations ......................................................................................................................... 52 5.1 Introduction (informative) .............................................................................................................52 5.2 Data declaration syntax..................................................................................................................52 5.3 Constants........................................................................................................................................52 Accellera SystemVerilog 3.1a Extensions to Verilog-2001 viii Copyright 2004 Accellera. All rights reserved . 5.4 Variables ........................................................................................................................................53 5.5 Scope and lifetime .........................................................................................................................54 5.6 Nets, regs, and logic.......................................................................................................................55 5.7 Signal aliasing................................................................................................................................56 5.8 Type compatibility .........................................................................................................................58 Section 6 Attributes....................................................................................................................................... 61 6.1 Introduction (informative) .............................................................................................................61 6.2 Default attribute type .....................................................................................................................61 Section 7 Operators and Expressions.......................................................................................................... 62 7.1 Introduction (informative) .............................................................................................................62 7.2 Operator syntax..............................................................................................................................62 7.3 Assignment operators ....................................................................................................................62 7.4 Operations on logic and bit types ..................................................................................................63 7.5 Wild equality and wild inequality..................................................................................................63 7.6 Real operators ................................................................................................................................64 7.7 Size.................................................................................................................................................64 7.8 Sign ................................................................................................................................................64 7.9 Operator precedence and associativity ..........................................................................................64 7.10 Built-in methods ............................................................................................................................65 7.11 Static Prefixes ................................................................................................................................66 7.12 Concatenation ................................................................................................................................67 7.13 Unpacked array expressions ..........................................................................................................67 7.14 Structure expressions .....................................................................................................................68 7.15 Tagged union expressions and member access..............................................................................70 7.16 Aggregate expressions ...................................................................................................................71 7.17 Operator overloading .....................................................................................................................72 7.18 Streaming operators (pack / unpack) .............................................................................................73 7.19 Conditional operator ......................................................................................................................77 7.20 Set membership..............................................................................................................................77 Section 8 Procedural Statements and Control Flow.................................................................................. 79 8.1 Introduction (informative) .............................................................................................................79 8.2 Statements ......................................................................................................................................79 8.3 Blocking and nonblocking assignments ........................................................................................80 8.4 Selection statements.......................................................................................................................81 8.5 Loop statements .............................................................................................................................87 8.6 Jump statements.............................................................................................................................89 8.7 Final blocks....................................................................................................................................89 8.8 Named blocks and statement labels ...............................................................................................90 8.9 Disable ...........................................................................................................................................90 8.10 Event control..................................................................................................................................91 8.11 Level-sensitive sequence controls .................................................................................................93 8.12 Procedural assign and deassign removal .......................................................................................94 Section 9 Processes........................................................................................................................................ 95 9.1 Introduction (informative) .............................................................................................................95 9.2 Combinational logic.......................................................................................................................95 9.3 Latched logic..................................................................................................................................96 9.4 Sequential logic..............................................................................................................................96 9.5 Continuous assignments ................................................................................................................96 9.6 fork...join........................................................................................................................................97 9.7 Process execution threads ..............................................................................................................98 Accellera Extensions to Verilog-2001 SystemVerilog 3.1a Copyright 2004 Accellera. All rights reserved. ix 9.8 Process control ...............................................................................................................................98 9.9 Fine-grain process control ...........................................................................................................100 Section 10 Tasks and Functions................................................................................................................... 102 10.1 Introduction (informative) ...........................................................................................................102 10.2 Tasks ............................................................................................................................................103 10.3 Functions......................................................................................................................................104 10.4 Task and function argument passing ...........................................................................................106 10.5 Import and export functions.........................................................................................................109 Section 11 Classes.......................................................................................................................................... 111 11.1 Introduction (informative) ...........................................................................................................111 11.2 Syntax ..........................................................................................................................................112 11.3 Overview......................................................................................................................................113 11.4 Objects (class instance)................................................................................................................113 11.5 Object properties..........................................................................................................................114 11.6 Object methods ............................................................................................................................114 11.7 Constructors .................................................................................................................................115 11.8 Static class properties...................................................................................................................116 11.9 Static methods..............................................................................................................................116 11.10 This ..............................................................................................................................................116 11.11 Assignment, re-naming and copying ...........................................................................................117 11.12 Inheritance and subclasses ...........................................................................................................118 11.13 Overridden members....................................................................................................................119 11.14 Super ............................................................................................................................................119 11.15 Casting .........................................................................................................................................120 11.16 Chaining constructors ..................................................................................................................120 11.17 Data hiding and encapsulation .....................................................................................................121 11.18 Constant class properties .............................................................................................................121 11.19 Abstract classes and virtual methods ...........................................................................................122 11.20 Polymorphism: dynamic method lookup.....................................................................................123 11.21 Class scope resolution operator :: ................................................................................................123 11.22 Out of block declarations .............................................................................................................124 11.23 Parameterized classes ..................................................................................................................125 11.24 Typedef class ...............................................................................................................................126 11.25 Classes and structures ..................................................................................................................126 11.26 Memory management ..................................................................................................................127 Section 12 Random Constraints .................................................................................................................. 128 12.1 Introduction (informative) ...........................................................................................................128 12.2 Overview......................................................................................................................................128 12.3 Random variables ........................................................................................................................131 12.4 Constraint blocks .........................................................................................................................132 12.5 Randomization methods ..............................................................................................................145 12.6 In-line constraints — randomize() with.......................................................................................147 12.7 Disabling random variables with rand_mode() ...........................................................................148 12.8 Controlling constraints with constraint_mode() ..........................................................................149 12.9 Dynamic constraint modification.................................................................................................150 12.10 In-line random variable control ...................................................................................................150 12.11 Randomization of scope variables — std::randomize()...............................................................151 12.12 Random number system functions and methods .........................................................................153 12.13Random stability ..........................................................................................................................154 12.14 Manually seeding randomize .......................................................................................................156 12.15 Random weighted case — randcase ............................................................................................157 Accellera SystemVerilog 3.1a Extensions to Verilog-2001 x Copyright 2004 Accellera. All rights reserved . 12.16 Random sequence generation — randsequence...........................................................................158 Section 13 Interprocess Synchronization and Communication................................................................ 166 13.1 Introduction (informative) ...........................................................................................................166 13.2 Semaphores ..................................................................................................................................166 13.3 Mailboxes.....................................................................................................................................167 13.4 Parameterized mailboxes .............................................................................................................170 13.5 Event ............................................................................................................................................171 13.6 Event sequencing: wait_order() ...................................................................................................172 13.7 Event variables.............................................................................................................................173 Section 14 Scheduling Semantics................................................................................................................. 176 14.1 Execution of a hardware model and its verification environment ...............................................176 14.2 Event simulation ..........................................................................................................................176 14.3 The stratified event scheduler ......................................................................................................176 14.4 The PLI callback control points...................................................................................................180 Section 15 Clocking Blocks .......................................................................................................................... 181 15.1 Introduction (informative) ...........................................................................................................181 15.2 Clocking block declaration ..........................................................................................................181 15.3 Input and output skews ................................................................................................................183 15.4 Hierarchical expressions ..............................................................................................................184 15.5 Signals in multiple clocking blocks .............................................................................................185 15.6 Clocking block scope and lifetime...............................................................................................185 15.7 Multiple clocking blocks example ...............................................................................................185 15.8 Interfaces and clocking blocks.....................................................................................................186 15.9 Clocking block events..................................................................................................................187 15.10 Cycle delay: ## ............................................................................................................................187 15.11 Default clocking...........................................................................................................................188 15.12 Input sampling .............................................................................................................................189 15.13 Synchronous events .....................................................................................................................189 15.14 Synchronous drives......................................................................................................................190 Section 16 Program Block............................................................................................................................ 193 16.1 Introduction (informative) ...........................................................................................................193 16.2 The program construct .................................................................................................................193 16.3 Multiple programs........................................................................................................................195 16.4 Eliminating testbench races .........................................................................................................195 16.5 Blocking tasks in cycle/event mode.............................................................................................196 16.6 Program control tasks ..................................................................................................................196 Section 17 Assertions ................................................................................................................................... 198 17.1 Introduction (informative) ...........................................................................................................198 17.2 Immediate assertions....................................................................................................................198 17.3 Concurrent assertions overview...................................................................................................200 17.4 Boolean expressions ....................................................................................................................201 17.5 Sequences.....................................................................................................................................203 17.6 Declaring sequences ....................................................................................................................206 17.7 Sequence operations ....................................................................................................................208 17.8 Manipulating data in a sequence..................................................................................................224 17.9 Calling subroutines on match of a sequence................................................................................228 17.10 System functions..........................................................................................................................229 17.11 Declaring properties.....................................................................................................................229 17.12 Multiple clock support .................................................................................................................240 Accellera Extensions to Verilog-2001 SystemVerilog 3.1a Copyright 2004 Accellera. All rights reserved. xi 17.13 Concurrent assertions...................................................................................................................246 17.14 Clock resolution ...........................................................................................................................252 17.15 Binding properties to scopes or instances....................................................................................258 17.16 The expect statement ...................................................................................................................259 Section 18 Hierarchy..................................................................................................................................... 261 18.1 Introduction (informative) ...........................................................................................................261 18.2 Packages.......................................................................................................................................261 18.3 Compilation unit support .............................................................................................................265 18.4 Top-level instance........................................................................................................................266 18.5 Module declarations.....................................................................................................................267 18.6 Nested modules............................................................................................................................267 18.7 Extern modules ............................................................................................................................269 18.8 Port declarations ..........................................................................................................................270 18.9 List of port expressions................................................................................................................271 18.10 Time unit and precision ...............................................................................................................271 18.11 Module instances .........................................................................................................................272 18.12 Port connection rules ...................................................................................................................276 18.13 Name spaces ................................................................................................................................277 18.14 Hierarchical names ......................................................................................................................278 Section 19 Interfaces ..................................................................................................................................... 279 19.1 Introduction (informative) ...........................................................................................................279 19.2 Interface syntax............................................................................................................................280 19.3 Ports in interfaces.........................................................................................................................284 19.4 Modports ......................................................................................................................................285 19.5 Interfaces and specify blocks .......................................................................................................291 19.6 Tasks and functions in interfaces.................................................................................................291 19.7 Parameterized interfaces ..............................................................................................................297 19.8 Virtual interfaces..........................................................................................................................299 19.9 Access to interface objects...........................................................................................................303 Section 20 Coverage...................................................................................................................................... 305 20.1 Introduction (informative) ...........................................................................................................305 20.2 Defining the coverage model: covergroup...................................................................................306 20.3 Using covergroup in classes ........................................................................................................308 20.4 Defining coverage points .............................................................................................................309 20.5 Defining cross coverage...............................................................................................................315 20.6 Specifying coverage options ........................................................................................................319 20.7 Predefined coverage methods ......................................................................................................324 20.8 Predefined coverage system tasks and functions .........................................................................324 20.9 Organization of option and type_option members ......................................................................324 Section 21 Parameters .................................................................................................................................. 326 21.1 Introduction (informative) ...........................................................................................................326 21.2 Parameter declaration syntax .......................................................................................................327 Section 22 Configuration Libraries............................................................................................................. 330 22.1 Introduction (informative) ...........................................................................................................330 22.2 Libraries .......................................................................................................................................330 Section 23 System Tasks and System Functions ........................................................................................ 331 23.1 Introduction (informative) ...........................................................................................................331 23.2 Elaboration-time typeof function.................................................................................................331 Accellera SystemVerilog 3.1a Extensions to Verilog-2001 xii Copyright 2004 Accellera. All rights reserved . 23.3 Typename function ......................................................................................................................331 23.4 Expression size system function ..................................................................................................332 23.5 Range system function.................................................................................................................333 23.6 Shortreal conversions...................................................................................................................333 23.7 Array querying system functions .................................................................................................334 23.8 Assertion severity system tasks ...................................................................................................335 23.9 Assertion control system tasks.....................................................................................................336 23.10 Assertion system functions ..........................................................................................................336 23.11 Random number system functions...............................................................................................337 23.12 Program control ...........................................................................................................................337 23.13 Coverage system functions ..........................................................................................................337 23.14 Enhancements to Verilog-2001 system tasks ..............................................................................337 23.15 $readmemb and $readmemh........................................................................................................338 23.16 $writememb and $writememh .....................................................................................................338 23.17 File format considerations for multi-dimensional unpacked arrays ............................................339 23.18 System task arguments for multi-dimensional unpacked arrays .................................................340 Section 24 VCD Data .................................................................................................................................... 342 Section 25 Compiler Directives.................................................................................................................... 343 25.1 Introduction (informative) ...........................................................................................................343 25.2 ‘define macros..............................................................................................................................343 25.3 `include ........................................................................................................................................344 Section 26 Features under consideration for removal from SystemVerilog ........................................... 345 26.1 Introduction (informative) ...........................................................................................................345 26.2 Defparam statements....................................................................................................................345 26.3 Procedural assign and deassign statements..................................................................................345 Section 27 Direct Programming Interface (DPI) ....................................................................................... 347 27.1 Overview......................................................................................................................................347 27.2 Two layers of the DPI ..................................................................................................................348 27.3 Global name space of imported and exported functions..............................................................349 27.4 Imported tasks and functions .......................................................................................................349 27.5 Calling imported functions ..........................................................................................................355 27.6 Exported functions .......................................................................................................................356 27.7 Exported tasks..............................................................................................................................357 27.8 Disabling DPI tasks and functions...............................................................................................357 Section 28 SystemVerilog Assertion API .................................................................................................... 359 28.1 Requirements ...............................................................................................................................359 28.2 Extensions to VPI enumerations..................................................................................................359 28.3 Static information ........................................................................................................................360 28.4 Dynamic information ...................................................................................................................363 28.5 Control functions .........................................................................................................................366 Section 29 SystemVerilog Coverage API .................................................................................................... 368 29.1 Requirements ...............................................................................................................................368 29.2 SystemVerilog real-time coverage access ...................................................................................369 29.3 FSM recognition ..........................................................................................................................374 29.4 VPI coverage extensions..............................................................................................................377 Section 30 SystemVerilog Data Read API .................................................................................................. 381 30.1 Introduction (informative) ...........................................................................................................381 Accellera Extensions to Verilog-2001 SystemVerilog 3.1a Copyright 2004 Accellera. All rights reserved. xiii 30.2 Requirements ...............................................................................................................................381 30.3 Extensions to VPI enumerations..................................................................................................382 30.4 VPI object type additions.............................................................................................................383 30.5 Object model diagrams ................................................................................................................385 30.6 Usage extensions to VPI routines ................................................................................................387 30.7 VPI routines added in SystemVerilog .........................................................................................388 30.8 Reading data ................................................................................................................................389 30.9 Optionally unloading the data......................................................................................................399 30.10 Reading data from multiple databases and/or different read library providers ...........................399 30.11VPI routines extended in SystemVerilog.....................................................................................402 30.12VPI routines added in SystemVerilog .........................................................................................403 Section 31 SystemVerilog VPI Object Model............................................................................................. 407 31.1 Introduction (informative) ...........................................................................................................407 31.2 Instance .......................................................................................................................................409 31.3 Interface ......................................................................................................................................410 31.4 Program........................................................................................................................................410 31.5 Module (supersedes IEEE 1364-2001 26.6.1) ............................................................................411 31.6 Modport ......................................................................................................................................412 31.7 Interface tf decl ............................................................................................................................412 31.8 Ports (supersedes IEEE 1364-2001 26.6.5) .................................................................................413 31.9 Ref Obj.........................................................................................................................................414 31.10 Variables (supersedes IEEE 1364-2001 section 26.6.8) .............................................................416 31.11 Var Select (supersedes IEEE 1364-2001 26.6.8).........................................................................418 31.12 Typespec ......................................................................................................................................419 31.13 Variable Drivers and Loads (supersedes IEEE 1364-2001 26.6.23) ...........................................421 31.14 Instance Arrays (supersedes IEEE 1364-2001 26.6.2) ................................................................421 31.15 Scope (supersedes IEEE 1364-2001 26.6.3) ...............................................................................422 31.16 IO Declaration (supersedes IEEE 1364-2001 26.6.4) .................................................................423 31.17 Clocking Block ...........................................................................................................................424 31.18 Class Object Definition................................................................................................................425 31.19 Constraint, constraint ordering, distribution, ...............................................................................426 31.20 Constraint expression...................................................................................................................427 31.21 Class Variables ...........................................................................................................................428 31.23 Named Events (supersedes IEEE 1364-2001 26.6.11) ................................................................430 31.24 Task, Function Declaration (supersedes IEEE 1364-2001 26.6.18)............................................431 31.25 Alias Statement ...........................................................................................................................432 31.26 Frames (supersedes IEEE 1364-2001 26.6.20)............................................................................433 31.27 Threads.........................................................................................................................................434 31.28 tf call (supersedes IEEE 1364-2001 26.6.19) ..............................................................................435 31.29 Module path, path term (supersedes IEEE 1364-2001 26.6.15) .................................................436 31.30 Concurrent assertions ..................................................................................................................437 31.31 Property Decl ..............................................................................................................................437 31.32 Property Specification .................................................................................................................438 31.33 Multiclock Sequence Expression ................................................................................................439 31.34 Sequence Declaration .................................................................................................................440 31.35 Sequence Expression ..................................................................................................................441 31.36 Attribute (supersedes IEEE 1364-2001 26.6.42) ........................................................................442 31.37 Atomic Statement (supersedes IEEE 1364-2001 26.6.27) .........................................................443 31.38 If, if else, return, case, do while (supersedes IEEE 1364-2001 26.6.35, 26.6.36).......................444 31.39 waits, disables, expect, foreach (supersedes IEEE 1364 26.6.38) ...............................................445 31.40 Simple expressions (supersedes IEEE 1364-2001 26.6.25) ........................................................446 31.41 Expressions (supersedes IEEE 1364-2001 26.6.26) ....................................................................447 31.42 Event control (supersedes IEEE 1364-2001 26.6.30)..................................................................448 Accellera SystemVerilog 3.1a Extensions to Verilog-2001 xiv Copyright 2004 Accellera. All rights reserved . 31.43 Event stmt (supersedes IEEE 1364-2001 26.6.27) .....................................................................448 31.44 Process (supersedes IEEE 1364-2001 26.6.27) ..........................................................................449 31.45 Assignment (supersedes IEEE 1364-2001 26.6.28) ...................................................................449 Annex A Formal Syntax.............................................................................................................................. 451 Annex B Keywords ...................................................................................................................................... 488 Annex C Std Package ................................................................................................................................. 490 Annex D Linked Lists................................................................................................................................. 492 Annex E DPI C-layer .................................................................................................................................. 498 Annex F Include files .................................................................................................................................. 523 Annex G Inclusion of Foreign Language Code ......................................................................................... 529 Annex H Formal Semantics of Concurrent Assertions ............................................................................ 533 Annex I sv_vpi_user.h................................................................................................................................ 544 Annex J Glossary ........................................................................................................................................ 553 Annex K Bibliography................................................................................................................................. 555 Index 557
Part I Basic Concepts 1 The Nature of Hardware and Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Introducing Hardware/Software Codesign .. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.1 Hardware .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.2 Software .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.3 Hardware and Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.4 Defining Hardware/Software Codesign . . . . . . . . . . . . . . . . . . . . . 11 1.2 The Quest for Energy Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.1 Relative Performance .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.2 Energy Efficiency .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3 The Driving Factors in Hardware/Software Codesign.. . . . . . . . . . . . . . . 15 1.4 The Hardware–Software Codesign Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4.1 The Platform Design Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.2 Application Mapping .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5 The Dualism of Hardware Design and Software Design .. . . . . . . . . . . . 20 1.6 More on Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.1 Abstraction Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.7 Concurrency and Parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.8 Summary.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.9 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.10 Problems .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2 Data Flow Modeling and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.1 The Need for Concurrent Models: An Example . . . . . . . . . . . . . . . . . . . . . . 33 2.1.1 Tokens, Actors, and Queues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.1.2 Firing Rates, Firing Rules, and Schedules. . . . . . . . . . . . . . . . . . . 38 2.1.3 Synchronous Data Flow Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.1.4 SDF Graphs are Determinate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2 Analyzing Synchronous Data Flow Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.2.1 Deriving Periodic Admissible Sequential Schedules . . . . . . . 41 2.2.2 Example: Euclid’s Algorithm as an SDF Graph . . . . . . . . . . . . 44 2.3 Control Flow Modeling and the Limitations of Data Flow Models . . 45 2.3.1 Emulating Control Flow with SDF Semantics . . . . . . . . . . . . . . 46 2.3.2 Extending SDF Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.4 Software Implementation of Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.4.1 Converting Queues and Actors into Software .. . . . . . . . . . . . . . 48 2.4.2 Sequential Targets with Dynamic Schedule .. . . . . . . . . . . . . . . . 51 2.4.3 Sequential Targets with Static Schedule . . . . . . . . . . . . . . . . . . . . . 57 2.5 Hardware Implementation of Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.5.1 Single-Rate SDF Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.5.2 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.5.3 Multirate Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.6 Summary.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.7 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.8 Problems .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3 Analysis of Control Flow and Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.1 Data and Control Edges of a C Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.2 Implementing Data and Control Edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.3 Contruction of the Control Flow Graph .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.4 Construction of the Data Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.5 Application: Translating C to Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.5.1 Designing the Datapath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.5.2 Designing the Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.6 Single-Assignment Programs .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.7 Summary.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.8 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.9 Problems .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Part II The Design Space of Custom Architectures 4 Finite State Machine with Datapath.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.1 Cycle-Based Bit-Parallel Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.1.1 Wires and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.1.2 Precision and Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.1.3 Hardware Mapping of Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.2 Hardware Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.3 Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 4.4 Finite State Machines with Datapath .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 4.4.1 Modeling .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 4.4.2 An FSMD is Not Unique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 4.4.3 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 4.5 Simulation and RTL Synthesis of FSMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 4.5.1 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 4.5.2 Code Generation and Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 4.6 Proper FSMD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 4.7 Language Mapping for FSMD by Example. . . . . . . . . . . . . . . . . . . . . . . . . . .119 4.7.1 GCD in GEZEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 4.7.2 GCD in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 4.7.3 GCD in VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 4.7.4 GCD in SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 4.8 Summary.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 4.9 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 4.10 Problems .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 5 Microprogrammed Architectures.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 5.1 Limitations of Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 5.1.1 State Explosion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 5.1.2 Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 5.1.3 Runtime Flexibility .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 5.2 Microprogrammed Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 5.3 Microinstruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 5.3.1 Jump Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 5.3.2 Command Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 5.4 The Microprogrammed Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 5.4.1 Datapath Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 5.4.2 Writing Microprograms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 5.5 Implementing a MicroprogrammedMachine . . . . . . . . . . . . . . . . . . . . . . . . .144 5.5.1 MicroinstructionWord Definition . . . . . . . . . . . . . . . . . . . . . . . . . . .144 5.6 Microprogram Interpreters .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 5.7 Microprogram Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 5.7.1 Microinstruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 5.7.2 Datapath Condition-Code Register . . . . . . . . . . . . . . . . . . . . . . . . . .157 5.7.3 Pipelined Next-Address Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 5.8 Picoblaze: A ContemporaryMicroprogram Controller.. . . . . . . . . . . . . .158 5.9 Summary.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 5.10 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 5.11 Problems .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 6 General-Purpose Embedded Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 6.1 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 6.1.1 The Toolchain of a Typical Microprocessor .. . . . . . . . . . . . . . . .166 6.1.2 From C to Assembly Instructions .. . . . . . . . . . . . . . . . . . . . . . . . . . .167 6.1.3 Simulating a C Program Executing on a Microprocessor . .170 6.2 The RISC Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 6.2.1 Control Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 6.2.2 Data Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 6.2.3 Structural Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 6.3 Program Organization .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 6.3.1 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 6.3.2 Variables in the Memory Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . .180 6.3.3 Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 6.3.4 Program Layout.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 6.4 Analyzing the Quality of Compiled Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 6.4.1 Analysis Based on Static Assembly Code . . . . . . . . . . . . . . . . . . .190 6.4.2 Analysis Based on Execution of Object Code. . . . . . . . . . . . . . .194 6.5 Summary.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 6.6 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 6.7 Problems .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 7 SystemOnChip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 7.1 The System-on-Chip Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 7.1.1 The Cast of Players . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 7.1.2 SoC Interfaces for Custom Hardware . . . . . . . . . . . . . . . . . . . . . . .207 7.2 Four Design Principles in SoC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . .209 7.2.1 Heterogeneous and Distributed Data Processing. . . . . . . . . . . .209 7.2.2 Heterogeneous and Distributed Communications.. . . . . . . . . .210 7.2.3 Heterogeneous and Distributed Storage . . . . . . . . . . . . . . . . . . . . .211 7.2.4 Hierarchical Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 7.3 Example: Portable Multimedia System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 7.4 SoC Modeling in GEZEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 7.4.1 An SoC with a StrongARM Core . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 7.4.2 Ping-Pong Buffer with an 8051 .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 7.5 Summary.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 7.6 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 7.7 Problems .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 Part III Hardware/Software Interfaces 8 On-Chip Busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 8.1 Connecting Hardware and Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 8.2 On-Chip Bus Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 8.2.1 Some Existing On-Chip Bus Systems . . . . . . . . . . . . . . . . . . . . . . .232 8.2.2 Bus Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 8.2.3 Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 8.2.4 Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 8.3 Bus Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 8.3.1 Simple Read and Write Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 8.3.2 Transfer Sizing and Endianess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 8.3.3 Improved Bus Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 8.4 Multimaster Bus Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 8.4.1 Bus Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 8.4.2 Bus Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 8.5 On-Chip Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 8.6 Summary.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 8.7 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 8.8 Problems .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 9 Hardware/Software Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 9.1 The Hardware/Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 9.2 Synchronization Schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 9.2.1 Synchronization Concepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 9.2.2 Semaphore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 9.2.3 One-Way and Two-Way Handshake . . . . . . . . . . . . . . . . . . . . . . . . .265 9.2.4 Blocking and Nonblocking Data-Transfer.. . . . . . . . . . . . . . . . . .267 9.3 Memory-Mapped Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 9.3.1 The Memory-Mapped Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 9.3.2 Mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 9.3.3 First-In First-Out Queues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 9.3.4 Slave and Master Handshakes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 9.3.5 Shared Memory .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 9.3.6 GEZEL Modeling of Memory-Mapped Interfaces.. . . . . . . . .275 9.4 Coprocessor Interfaces .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 9.4.1 Tight and Loose Coupling.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 9.4.2 The Fast Simplex Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 9.4.3 The LEON-3 Floating Point Coprocessor Interface . . . . . . . .284 9.5 Custom-Instruction Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 9.5.1 ASIP Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 9.5.2 Example: Endianess Byte-Ordering Processor . . . . . . . . . . . . . .288 9.5.3 Finding Good ASIP Instructions .. . . . . . . . . . . . . . . . . . . . . . . . . . . .293 9.6 Summary.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 9.7 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 9.8 Problems .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 10 Coprocessor Control Shell Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 10.1 The Coprocessor Control Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 10.1.1 Functions of the Coprocessor Control Shell. . . . . . . . . . . . . . . . .303 10.1.2 Layout of the Coprocessor Control Shell . . . . . . . . . . . . . . . . . . . .305 10.1.3 Communication-Constrained vs. Computation-Constrained Coprocessors . . . . . . . . . . . . . . . . . . . .306 10.2 Data Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 10.2.1 Flexible Addressing Mechanisms. . . . . . . . . . . . . . . . . . . . . . . . . . . .308 10.2.2 Multiplexing and Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 10.3 Control Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310 10.3.1 Hierarchical Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 10.3.2 Control of Internal Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313 10.4 Programmer’sModel = Control Design + Data Design . . . . . . . . . . . . . .317 10.4.1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 10.4.2 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 10.5 Example: AES Encryption Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 10.5.1 Control Shell Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 10.5.2 Programmer’sModel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 10.5.3 Software Driver Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 10.5.4 Control Shell Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324 10.5.5 System Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 10.6 Summary.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 10.7 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 10.8 Problems .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330 Part IV Applications 11 Trivium Crypto-Coprocessor.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 11.1 The Trivium Stream Cipher Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 11.1.1 Stream Ciphers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 11.1.2 Trivium.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 11.1.3 Hardware Mapping of Trivium . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 11.1.4 A Hardware Testbench for Trivium. . . . . . . . . . . . . . . . . . . . . . . . . .344 11.2 Trivium for 8-bit Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344 11.2.1 Overall Design of the 8051 Coprocessor . . . . . . . . . . . . . . . . . . . .345 11.2.2 Hardware Platform of the 8051 Coprocessor.. . . . . . . . . . . . . . .346 11.2.3 Software Driver for 8051 .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350 11.3 Trivium for 32-bit Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 11.3.1 Hardware Platform Using Memory-mapped Interfaces.. . . .355 11.3.2 Software Driver Using Memory-mapped Interfaces . . . . . . . .358 11.3.3 Hardware Platform Using a Custom-Instruction Interface .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 11.3.4 Software Driver for a Custom-Instruction Interface . . . . . . . .364 11.4 Summary.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366 11.5 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367 11.6 Problems .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367 12 CORDIC Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 12.1 The Coordinate Rotation Digital Computer Algorithm . . . . . . . . . . . . . .369 12.1.1 The Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 12.1.2 Reference Implementation in C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 12.2 A Hardware Coprocessor for CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373 12.2.1 A CORDIC Kernel in Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373 12.2.2 A Control Shell for Fast-Simplex-Link Coprocessors . . . . . .376 12.3 An FPGA Prototype of the CORDIC Coprocessor . . . . . . . . . . . . . . . . . . .379 12.4 Handling Large Amounts of Rotations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 12.5 Summary.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 12.6 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 12.7 Problems .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
### 回答1: "Object reference not set to an instance of an object" 意思是未将对象引用设置到对象的实例。这通常是因为在使用未初始化的对象引用变量进行操作时发生的。 ### 回答2: nullreferenceexception: object 是程序中常见的错误类型之一,通常是由于代码中引用了一个 null 对象而导致的。 在程序中,当对象被创建时,它会在内存中分配一段空间,对象的属性和方法也会被赋予初始值,即使不为其属性赋值,它们也会被设置一个默认值。然而,当一个对象的值被设置为 null,它就没有任何有效的值了,此时如果再尝试读取其属性或调用其方法就会引发 nullreferenceexception: object 错误。 一般情况下,解决这种错误需要先判断对象是否为 null,再根据情况进行相应的处理,例如可以通过新建对象来替换 null 对象的引用,或者直接返回 null 停止代码执行。在查找 null 引用时可以使用 Visual Studio 中的调试工具,在程序执行到出错的代码处添加断点,单步调试来定位问题代码。 总之,nullreferenceexception: object 错误是开发过程中难免会遇到的问题,正确的应对方式是注意代码的逻辑和对对象的引用进行合理的判断和处理。 ### 回答3: NullReferenceExceptionC#编程中常见的一个错误,它表示了一个对象为null时所引发的异常。在程序中,我们常常使用对象来存储数据或进行操作,而当我们试图去访问一个空对象时,就会引发NullReferenceException异常。 在C#中,对象在声明之后必须进行实例化,否则就是一个空对象。在调用该对象的属性和方法时,就会发生NullReferenceException异常。这是因为null值表示一个缺失的对象,它没有任何属性或方法。因此,在使用对象时,我们必须确保它已经被正确地实例化,并且不为null。 造成NullReferenceException异常的原因往往是由于程序员在编写程序时没有正确的检查对象的状态。例如,在调用对象的方法前没有进行非空判断,或者调用一个尚未实例化的对象。 例如: ``` string str = null; int length = str.Length; //NullReferenceException异常 ``` 上述代码中,我们尝试获取一个空字符串的长度,此时会发生NullReferenceException异常,因为字符串对象str为null,没有任何属性或方法可供使用。 为了避免NullReferenceException异常,我们需要在程序中进行适当的非空判断。例如,在访问对象的属性和方法前,需要先判断该对象是否为null。如果对象为null,我们可以选择抛出异常或者进行错误处理。在更大的项目中,可以使用代码分析工具来发现潜在的NullReferenceException问题。 总之,NullReferenceExceptionC#编程中是一个常见的异常,出现的原因通常是由于没有正确地检查对象的状态。因此,编写高质量的C#代码需要我们时刻注意对象的状态,以避免这种异常的发生。

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