排序（Verilog）

RTL代码：

module sort(
	input clk,
	input rst_n,
	input sort_start,
	
	output reg sort_end,
	output reg [7:0]data_out
);
	//输入要排序的数组
	wire [7:0]data_in[7:0];
	
	assign data_in[0] = 8'd5;
	assign data_in[1] = 8'd8;
	assign data_in[2] = 8'd9;
	assign data_in[3] = 8'd1;
	assign data_in[4] = 8'd7;
	assign data_in[5] = 8'd9;
	assign data_in[6] = 8'd0;
	assign data_in[7] = 8'd0;
	
	parameter len = 8;
	reg [3:0]i;
	reg [3:0]j;
	reg en;
	
	//控制比较使能信号
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			en <= 1'b0;
		else if(sort_start)
			en <= 1'b1;
		else if(sort_end)
			en <= 1'b0;
		else
			en <= en;
	end
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			sort_end <= 1'b0;
		else if((j == len-1) && (i == len-1-j))
			sort_end <= 1'b1;
		else
			sort_end <= 1'b0;
	end
	
	//内部循环
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			i <= 'd0;
		else if(en)begin
			if(i < len-1-j)
				i <= i + 1'b1;
			else
				i <= 'd0;
		end
		else
			i <= 'd0;
	end
	
	
	reg [7:0]data_r[7:0];
	reg [7:0]temp;
	
	//数据比较
	always@(*)begin
		if(!rst_n)begin
			data_r[0] = data_in[0]; 
			data_r[1] = data_in[1]; 
			data_r[2] = data_in[2]; 
			data_r[3] = data_in[3]; 
			data_r[4] = data_in[4]; 
			data_r[5] = data_in[5]; 
			data_r[6] = data_in[6]; 
			data_r[7] = data_in[7]; 
			temp = 'd0;
		end
		else if(data_r[i] > data_r[i+1])begin
			temp = data_r[i];
			data_r[i] = data_r[i+1];
			data_r[i+1] = temp;
		end
		else begin
			temp = temp;
			data_r[i] =data_r[i];
			data_r[i+1] = data_r[i+1];
		end			
	end
	
	//外层循环
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			j <= 'd0;
		else if(en)begin
			if(i == len-1-j)
				j <= j + 1'b1;
			else
				j <= j;
		end
		else
			j <= 'd0;
	end
	
	reg end_en;
	reg [2:0]cnt;
	
	//比较之后数据输出
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			end_en <= 1'b0;
		else if(sort_end)
			end_en <= 1'b1;
		else if(cnt == 'd7)
			end_en <= 1'b0;
		else
			end_en <= end_en;
	end
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			cnt <= 'd0;
		else if(end_en)begin
			if(cnt == 'd7)
				cnt <= 'd0;
			else
				cnt <= cnt + 1'b1;
		end
		else
			cnt <= 'd0;
	end
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			data_out <= 'd0; 
		else if(end_en)
			data_out <= data_r[cnt]; 
		else
			data_out <= 'd0; 
	end
	

endmodule

RTL仿真：

`timescale 1ns / 1ps

module sort_tb;

    reg clk;
	reg rst_n;
	reg sort_start;
	
	wire sort_end;
	wire [7:0]data_out;
	
    sort sort_inst(
	   .clk        (clk),
	   .rst_n      (rst_n),
	   .sort_start (sort_start),
	
	   .sort_end   (sort_end),
       .data_out   (data_out)
);

    initial clk = 0;
    always#10 clk = ~clk;
    
    initial begin
        rst_n = 0;
        sort_start = 0;
        #200;
        rst_n = 1;
        #200;
        sort_start = 1;
        #20;
        sort_start = 0;
    end

endmodule

仿真波形：