verilog实现冒泡法排序

verilog实现冒泡法排序

// 冒泡法排序 用verilog实现
module sort(
	input clk,
	input rst_n,
	input [3:0] data0,data1,data2,data3,data4,data5,data6,data7,data8,data9,
	input load,
	output  complete
//	output reg [3:0] data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7,data_out8,data_out9
	);
reg [3:0] data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7,data_out8,data_out9;	
parameter idle=2'b00,
		  loading=2'b01,
		  sorting=2'b10,
		  comp=2'b11;
reg [1:0] state, nstate;
reg [4:0] cnt;

// 状态转换
always@(posedge clk or negedge rst_n)
	if(!rst_n)
		state<=idle;
	else 
		state<=nstate;
		
// 计数cnt， 9个数据需要排序的clk为 18；	
always@(posedge clk or negedge rst_n)
	if(!rst_n)
		cnt<=0;
	else case(state)
	sorting: cnt<=cnt+1;
	default: cnt<=0;
	endcase

// 排序，若相邻数，前者大于后者，交换；	
always@(posedge clk or negedge rst_n)
	if(!r