Verilog HDL：PCM编码器设计（Testbench5）

PCM_ENCODER_TEST_5.v

/********************************************************************************* 
  *Copyright(C), IC Design
  *FileName: PCM_ENCODER_TEST_5.v
  *Author: Yue Shipeng
  *Version: 9.0
  *Date: 2023.01.18 02:00
  *Description: TESTBENCH FOR PCM_ENCODER
  *History: Notepad++ version
**********************************************************************************/  

/********************************************************************************* 
PCM ENCODER TEST 5
**********************************************************************************/

`timescale 10ns/1ns

module PCM_ENCODER_TEST_5;

reg clk;
reg rst;
reg [7:0] din;
reg [3:0] N;
reg INE;
wire dout;

parameter half_cycle = 10;

PCM_ENCODER ut5(
	.clk(clk),
	.rst(rst),
	.din(din),
	.N(N),
	.INE(INE),
	.dout(dout)
);

initial begin
	clk = 0;
	forever begin
		clk = # half_cycle ~ clk;
	end
end

initial begin
	rst = 1;
	# (1 * half_cycle) rst = 0;
	# (2 * half_cycle) rst = 1;
end

initial

	// the initial set of input signal;
	din <= 0;
	N <= 0;
	INE <= 0;
	
	// the 3 Byte data is received;
	
	// 4A, 0100_1010;
	repeat (5) @ (posedge clk);
	din <= 8'h4A;
	N <= 4'd2;
	INE <= 1;
	
	// 5B, 0101_1011;
	repeat (1) @ (posedge clk);
	din <= 8'h5B;
	N <= 0;
	INE <= 0;

	// 6C, 0110_1100;
	repeat (1) @ (posedge clk);
	din <= 8'h6C;
	
	repeat (1) @ (posedge clk);
	din <= 0;
	
	repeat (2800) @ (posedge clk);
	$finish;
	
end

initial begin
	$fsdbDumpfile("./verdiFsdb/PCM_ENCODER_TEST_5.fsdb");
	$fsdbDumpvars(0);
	$fsdbDumpMDA;
end

endmodule

Experiment Result