位宽转换电路

位宽转换电路

8-12

1 module width_change_8to12
2 (
3 input clk , // system clock 50Mhz on board
4 input rst_n , // system rst, low active
5 input a_vld , // input a_vld
6 input [7:0] a , // input a
7 output reg b_vld , // output b_vld
8 output reg [11:0] b // output b
9 );
10
11 // reg define
12
13 reg [1:0] vld_cnt ;
14 reg [7:0] a_lock ;
15
16 //===========================================================================
17 // ------------------------- MAIN CODE -------------------------------------
18 //===========================================================================
19
20 always @ (posedge clk or negedge rst_n) begin
21 if (rst_n == 1'b0)
22 vld_cnt <= 2'b0 ;
23 else if ( a_vld == 1'b1 ) begin
24 if ( vld_cnt == 2'd2 )
25 vld_cnt <= 2'b0 ;
26 else
27 vld_cnt <= vld_cnt + 2'b1 ;
28 end
29 else ;
30 end
31
32 always @ (posedge clk or negedge rst_n) begin
33 if (rst_n == 1'b0)
34 a_lock <= 8'b0 ;
35 else if ( a_vld == 1'b1 )
36 a_lock <= a ;
37 end
38
39 always @ (posedge clk or negedge rst_n) begin
40 if (rst_n == 1'b0)
41 b_vld <= 1'b0 ;
42 else if ( a_vld == 1'b1 && vld_cnt == 2'd1 )
43 b_vld <= 1'b1 ;
44 else if ( a_vld == 1'b1 && vld_cnt == 2'd2 )
45 b_vld <= 1'b1 ;
46 else
47 b_vld <= 1'b0 ;
48 end
49
50 always @ (posedge clk or negedge rst_n) begin
51 if (rst_n == 1'b0)
52 b <= 12'b0 ;
53 else if ( a_vld == 1'b1 && vld_cnt == 2'd1 )
54 b <= { a_lock, a[7:4] } ;
55 else if ( a_vld == 1'b1 && vld_cnt == 2'd2 )
56 b <= { a_lock[3:0], a} ;
57 end
58
59 endmodule

8-16

1 module width_change_8to16
2 (
3 input clk , // system clock 50Mhz on board
4 input rst_n , // system rst, low active
5 input a_vld , // input a_vld
6 input [7:0] a , // input a
7 output reg b_vld , // output b_vld
8 output reg [15:0] b // output b
9 );
10
11 // reg define
12
13 reg flag ;
14 reg [7:0] a_lock ;
15
16 //=======================================================
17 // ------------------------- MAIN CODE -----------------
18 //=======================================================
19
20 always @ (posedge clk or negedge rst_n) begin
21 if (rst_n == 1'b0)
22 flag <= 1'b0 ;
23 else if ( a_vld == 1'b1 )
24 flag <= ~flag ;
25 end
26
27 always @ (posedge clk or negedge rst_n) begin
28 if (rst_n == 1'b0)
29 a_lock <= 8'b0 ;
30 else if ( a_vld == 1'b1 )
31 a_lock <= a ;
32 end
33
34 always @ (posedge clk or negedge rst_n) begin
35 if (rst_n == 1'b0)
36 b_vld <= 1'b0 ;
37 else if ( a_vld == 1'b1 && flag == 1'b1 )
38 b_vld <= 1'b1 ; // 产生 vld 信息
39 else
40 b_vld <= 1'b0 ;
41 end
42
43 always @ (posedge clk or negedge rst_n) begin
44 if (rst_n == 1'b0)
45 b <= 16'b0 ;
46 else if ( a_vld == 1'b1 && flag == 1'b1 )
47 b <= { a_lock, a } ; // 拼接数据
48 end
49
50 endmodule