项目场景:
更改了一些模块,涉及时钟的时候报错
问题描述
[BD 41-237] Bus Interface property CLK_DOMAIN does not match between /send_out/channel0/lite2fifo2ctrl_0/S_AXI(top_xdma_ddr4_0_0_c0_ddr4_ui_clk) and /cpu/axi_interconnect_1/m00_couplers/auto_cc/M_AXI(top_xdma_tx_clk_in)
[BD 41-237] Bus Interface property CLK_DOMAIN does not match between /send_out/channel1/M_RegLite_0/S_AXI(top_xdma_ddr4_0_0_c0_ddr4_ui_clk) and /cpu/axi_interconnect_1/m01_couplers/auto_cc/M_AXI(top_xdma_tx_clk_in)
原因分析:
1.没有删去引脚
2.时钟连接不对
3.端口时钟设置不对