DC lab3

最新推荐文章于 2024-10-13 19:52:54 发布

younger955

最新推荐文章于 2024-10-13 19:52:54 发布

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本文链接：https://blog.csdn.net/weixin_44781750/article/details/137126301

版权

根据约束写出约束文件，并对RTL文件进行逻辑综合

根据以上约束说明可知，

Clock Definition：

1.时钟周期为1/333.33MHz，即3ns;

2.最大外部延时，0.7ns（700ps）;（外部latency）

3.clock到寄存器的最大延时为300ps+/-30ps，因为+/-30ps，可知clock skew是60ps；（内部latency，总共latency1ns）

4.clock jitter考虑悲观的情况是-40ps；

5.margin是50ps， $uncertian=skew+jitter+margin=60+40+50=150ps$ ;

6.clock transition是120ps；

Register Setup Time：

1.寄存器的setup时间是0.2ns；

Input Ports:

1.从端口data1/data2通过组合逻辑S的最大延时是2.2ns；（为了约束S的延时是2.2ns，需要设置input delay，那么 $Tinputdelay\leq T-Ts-Tuncer-Tsetup=3-2.2-0.15-0.2=0.45$ ）

2.F3到达sel端口的最晚到达时间是1.4ns（绝对时间）；（input delay是相对时间=外部延时1.4ns-相对延时0.7ns）

Output Ports:
1.out1端口的最大外部组合逻辑时间是420ps，F6的setup时间是80ps，output delay=420ps+80ps=500ps； $Toutput delay+Tskew+Tinternal_delay=T$

2.最大的内部delay到out2是810ps,那么out2的output delay应该是 $Toutput_delay\leqslant T-Tinputdelay-Tskew=3-0.81-0.15=2.04$

3.out3的外部output delay=0.4ns；

Conbinational Logic：
1.set_max_delay 0.4 -from Cin1* -to Cout* （伪命令）

2.set_max_delay 0.4 -from Cin2* -to Cout* （伪命令）

$T-Tcomb-Tskew=0.4ns\geqslant Tinputdelay+Toutputdelay$ ,一般这时候Tout和Tin各设0.2ns

写约束文件，MY_DESIGN.con

###################################
#                                 #
#   UNITS                         #
#                                 #
###################################

# The unit of time in this library is 1ns 
#

###################################
#                                 #
#   CLEAN-UP                      #
#                                 #
###################################

# Remove any existing constraints and attributes
#
reset_design


###################################
#                                 #
#   CLOCK DEFINITION              #
#                                 #
###################################

# A 333Mhz clock is a 3.0ns period:
#
create_clock -period 3.0 [get_ports clk]


# The maximum clock source latency is 700ps or 0.7ns
#
set_clock_latency -source  -max 0.7 [get_clocks clk] 


# The maximum clock network latency is 300ps or 0.3 ns:
#
set_clock_latency -max 0.3 [get_clocks clk]


# Add 60ps of uncertainty to model skew:
#   The spec says: "The maximum insertion delay from the clock port
#   to all the register clock PINS is 300ps +/- 30ps. PINS is the key word here!
#   The +/-30ps clock insertion delay variation to register clock PINS
#   means that, worst case, the launching clock edge can be late by +30ps,
#   and the capture edge can be early by -30ps.
# Add 40ps to model jitter: Here we do NOT double the 40ps, because the spec
#   says that the PERIOD fluctuates +/- 40, so the worst case is when the
#   period is -40.
# Add 50ps for setup margin.
#
# This equals 150ps or 0.15 ns of total uncertainty.
#
set_clock_uncertainty -setup 0.15 [get_clocks clk]


# The maximum clock transition is 120ps or 0.12ns
#
set_clock_transition -max 0.12 [get_clocks clk]


###################################
#                                 #
#   INPUT PATH TIMING             #
#                                 #
###################################

# The maximum "input delay" (external) on ports data1 and data2 is: 
# clock period - clock uncertainty - delay of S - register setup time = 
#     3.0      -      0.15         -     2.2   -      0.2            = 0.45ns
# 
set_input_delay -max  0.45 -clock clk [get_ports data*]  


# The latest arrival time at port sel is 1.4ns (absolute time). The total clock insertion delay or latency to the external 
# registers is 700ps + 300ps or 1.0ns. Therefore, the relative input delay on the port is 1.4 -1.0 = 0.4ns
#
set_input_delay -max  0.4 -clock clk [get_ports sel]


###################################
#                                 #
#   OUTPUT PATH TIMING            #
#                                 #
###################################

# The output delay at port out1 is 420ps + 80ps = 500ps or 0.5ns
#
set_output_delay -max  0.5 -clock clk [get_ports out1*]


# The internal delay to out2 is 810ps. The external capturing clock edge happens 3ns after the launch edge, 
# minus the uncertainty of 0.15ns, or 2.85ns after launch. To constrain the internal delay to 0.81ns the 
# output delay must therefore be constrained to 2.85ns - 0.81ns = 2.04ns.
#
set_output_delay -max 2.04  -clock clk [get_ports out2*]


# The setup time requirement on port out3 is 400ps or 0.4ns with respect to the capturing register's clock. 
# This is, by definition, the "set_output_delay" value
#
set_output_delay -max  0.4 -clock clk [get_ports out3*] 


###################################
#                                 #
#   COMBINATIONAL PATH TIMING     #
#                                 #
###################################

# The maximum delay through the combinational logic is 2.45ns. This can be constrained by pretending that there are 
# launching registers on the input ports Cin1 and Cin2 and capturing registers on the output port Cout, and applying 
# corresponding input and output delays. The sum of the external input and output delay values must be equal to the 
# clock period minus the clock uncertainty minus the maximum combo delay = 3ns - 0.15ns - 2.45ns = 0.4ns. 
# This means that the input and output delay values can be 0.4 and 0.0, or 0.2 and 0.2, or 0.1 and 0.3, etc., respectively.
#
set_input_delay -max 0.3 -clock clk [get_ports Cin*]
set_output_delay -max 0.1 -clock clk [get_ports Cout*]

#use max delay
#set_max_delay 0.4 -from [get_ports Cin*] -to [get_ports Cout*]

查看dc，打开dc_shell，读库打印单位信息

查看库的名字，sc_max.db是库文件

report库中的信息，可知时间单位是1ns，电容单位是1pf

可把库的信息保存到lib.rpt

report_lib cb13fs120_tsmc_max >lib.rpt

开始综合

read_verilog rtl/MY_DESIGN.v   #读rtl文件
current_design TOP  #如果有顶层要定义顶层
source scripts/MY_DESIGN.con   #读约束，没有报任何信息就是没错
#source scripts/MY_DESIGN.con -verbose -echo  所有执行的命令都返回一个信息，如果是1就没问题
check_timing   #检查时序是否完整，这里有warning说21个input端口只有部分有input delay，这是因为只设了max,没有设hold的min时间
compile_ultra #跑综合
report_qor    #报告时钟，面积等信息
write -format verilog -hier -output MY_DESIGN.gv
write -format ddc -hier -output MY_DESIGN.ddc

读出综合后针对网表的约束（注意这里和RTL的约束不一样，例如网表中有些cell RTL中没有）

write_script -output scripts/MY_DESIGN.post.sdc

对比综合前后约束的不同，没有通配符，写的更完整

###################################################################

# Created by write_script -format dctcl on Tue Apr  2 22:46:13 2024

###################################################################

# Set the current_design #
current_design MY_DESIGN

set_units -time ns -resistance kOhm -capacitance pF -voltage V -current uA
remove_wire_load_model
set_local_link_library {sc_max.db}
set_register_merging [current_design] 17
set_map_only [get_cells intadd_0/U4] 
set_map_only [get_cells intadd_0/U3] 
set_map_only [get_cells intadd_2/U2] 
set_map_only [get_cells intadd_1/U4] 
set_map_only [get_cells intadd_1/U3] 
set_map_only [get_cells intadd_2/U3] 
set_map_only [get_cells intadd_1/U2] 
set_map_only [get_cells intadd_2/U4] 
set_map_only [get_cells intadd_0/U2] 
set_register_merging [get_cells {R3_reg[1]}] 17
set_register_merging [get_cells {R3_reg[3]}] 17
set_register_merging [get_cells {R3_reg[2]}] 17
set_register_merging [get_cells {R3_reg[4]}] 17
set_register_merging [get_cells {R1_reg[0]}] 17
set_register_merging [get_cells {R1_reg[1]}] 17
set_register_merging [get_cells {R1_reg[2]}] 17
set_register_merging [get_cells {R1_reg[3]}] 17
set_register_merging [get_cells {R1_reg[4]}] 17
set_register_merging [get_cells {R2_reg[0]}] 17
set_register_merging [get_cells {R2_reg[1]}] 17
set_register_merging [get_cells {R2_reg[2]}] 17
set_register_merging [get_cells {R2_reg[3]}] 17
set_register_merging [get_cells {R2_reg[4]}] 17
set_register_merging [get_cells {R4_reg[0]}] 17
set_register_merging [get_cells {R4_reg[1]}] 17
set_register_merging [get_cells {R4_reg[2]}] 17
set_register_merging [get_cells {R4_reg[3]}] 17
set_register_merging [get_cells {R4_reg[4]}] 17
set_switching_activity -period 1 -toggle_rate 0.0333333 -static_probability    \
0.5 [get_ports {Cin1[4]}]
create_clock [get_ports clk]  -period 3  -waveform {0 1.5}
set_clock_latency -max 0.3  [get_clocks clk]
set_clock_latency -source -max 0.7  [get_clocks clk]
set_clock_uncertainty -setup 0.15  [get_clocks clk]
set_clock_transition -max -rise 0.12 [get_clocks clk]
set_clock_transition -max -fall 0.12 [get_clocks clk]
set_input_delay -clock clk  -max 0.45  [get_ports {data1[4]}]
set_input_delay -clock clk  -max 0.45  [get_ports {data1[3]}]
set_input_delay -clock clk  -max 0.45  [get_ports {data1[2]}]
set_input_delay -clock clk  -max 0.45  [get_ports {data1[1]}]
set_input_delay -clock clk  -max 0.45  [get_ports {data1[0]}]
set_input_delay -clock clk  -max 0.45  [get_ports {data2[4]}]
set_input_delay -clock clk  -max 0.45  [get_ports {data2[3]}]
set_input_delay -clock clk  -max 0.45  [get_ports {data2[2]}]
set_input_delay -clock clk  -max 0.45  [get_ports {data2[1]}]
set_input_delay -clock clk  -max 0.45  [get_ports {data2[0]}]
set_input_delay -clock clk  -max 0.4  [get_ports sel]
set_input_delay -clock clk  -max 0.3  [get_ports {Cin1[4]}]
set_input_delay -clock clk  -max 0.3  [get_ports {Cin1[3]}]
set_input_delay -clock clk  -max 0.3  [get_ports {Cin1[2]}]
set_input_delay -clock clk  -max 0.3  [get_ports {Cin1[1]}]
set_input_delay -clock clk  -max 0.3  [get_ports {Cin1[0]}]
set_input_delay -clock clk  -max 0.3  [get_ports {Cin2[4]}]
set_input_delay -clock clk  -max 0.3  [get_ports {Cin2[3]}]
set_input_delay -clock clk  -max 0.3  [get_ports {Cin2[2]}]
set_input_delay -clock clk  -max 0.3  [get_ports {Cin2[1]}]
set_input_delay -clock clk  -max 0.3  [get_ports {Cin2[0]}]
set_output_delay -clock clk  -max 0.5  [get_ports {out1[4]}]
set_output_delay -clock clk  -max 0.5  [get_ports {out1[3]}]
set_output_delay -clock clk  -max 0.5  [get_ports {out1[2]}]
set_output_delay -clock clk  -max 0.5  [get_ports {out1[1]}]
set_output_delay -clock clk  -max 0.5  [get_ports {out1[0]}]
set_output_delay -clock clk  -max 2.04  [get_ports {out2[4]}]
set_output_delay -clock clk  -max 2.04  [get_ports {out2[3]}]
set_output_delay -clock clk  -max 2.04  [get_ports {out2[2]}]
set_output_delay -clock clk  -max 2.04  [get_ports {out2[1]}]
set_output_delay -clock clk  -max 2.04  [get_ports {out2[0]}]
set_output_delay -clock clk  -max 0.4  [get_ports {out3[4]}]
set_output_delay -clock clk  -max 0.4  [get_ports {out3[3]}]
set_output_delay -clock clk  -max 0.4  [get_ports {out3[2]}]
set_output_delay -clock clk  -max 0.4  [get_ports {out3[1]}]
set_output_delay -clock clk  -max 0.4  [get_ports {out3[0]}]
set_output_delay -clock clk  -max 0.1  [get_ports {Cout[4]}]
set_output_delay -clock clk  -max 0.1  [get_ports {Cout[3]}]
set_output_delay -clock clk  -max 0.1  [get_ports {Cout[2]}]
set_output_delay -clock clk  -max 0.1  [get_ports {Cout[1]}]
set_output_delay -clock clk  -max 0.1  [get_ports {Cout[0]}]