DC LAB4

Target

• Define Design Compiler environmental attributes based on a provided design schematic and specification
• Apply the attributes to a design
• Verify the applied attributes

1.set environmental attributes

1.1 set input port attribute (remove clk)

• 对于input port有三种方法指定属性
  • 1.set_drive
  • 2.set_driveing_cell
  • 3.set_input_transition

1.2 set output port attribute

• 对于output port通过如下方法指定属性
  • set_load
    

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1.3 operation_condition

2. Check MY_DESIGN.con Syntx(检查约束文件tcl语法)

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3. 启动DC 读入设计

3.1 dc_shell-t -64bit -topo

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3.2 read_file -format verilog (这种方法读入设计不需要指定TOP)

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3.3 link

4. check_design

5.Apply the constraints file

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6.report_port -v

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6.1 input port

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6.2 output port

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7. write unmapped/xxx.ddc