DC LAB3

1.启动DC

dc_shell-t -64bit -topo | tee -i lab3.log

1.1 check_library

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2. read_db（读取标准单元库文件）

2.1 list_libs(不read_db直接read_verilog再list_libs也是下面的效果)

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2.2 Generate a library report file

dc_shell-topo> redirect -help
Usage: redirect    # Redirect output of a command to a file
        [-append]              (Append output to the file)
        [-tee]                 (Tee output to the current output stream)
        [-file]                (Output to a file (default))
        [-compress]            (Compress when writing to file)
        [-variable]            (Output to a variable)
        [-channel]             (Output to a Tcl channel)
        [-bg]                  (Execute redirected cmd string in background. PID of the background process is returned when this option is used)
        [-max_cores max_cores] (Number of cores to use to execute the command in background: 
                                Range: 1 to 8)
        target                 (Name of file/variable target for redirect)
        command_string         (Command to redirect.  Should be in braces {}.)

redirect -file lib.rpt {report_lib cb13fs120_tsmc_max}

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2.3 redirect -file lib.rpt {report_lib cb13fs120_tsmc_max}

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3. 检查约束文件语法

dcprocheck scripts/MY_DESIGN.con（在linux终端）

4.读入设计

read_verilog MY_DESIGN.v
current_design MY_DESIGN 
link
check_design

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The check_design command checks the internal representation of the current design
for consistency, and issues error and warning messages as appropriate.

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5. Apply the constraints file

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• 约束文件第一句推荐Reset Design
  

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5.1 check_timing

• 只检查setup，只设置了max delay，所以有这个warning，可以不用care
  

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5.2 report_clock

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5.3 report_clock -skew

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5.4 report_port verbose

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6.set input delay

6.1 sequential logic

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• launch clock path + cq + q-sel = 1.4us
• launch clock path(source latency 700ps + network latency 300ps ) + input delay = 1.4us
• input delay = 0.4us
  

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6.2 combinational logic（in2out）

• Tinput delay +Tcomb（2.45us） = T - Tuncertainly（0.15us） - Toutput delay
  
  

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7.set output delay

7.1 sequential logic

7.2 combinational logic（in2out）

8.write_script 导出MY_DESIGN.cons应用的约束

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9. write unmapped/ddc

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10.遇到不会的命令man&help

10.1 启动DC后MAN CMD

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10.2 启动DC后CMD -HELP（在dc_shell终端）

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11. 在dc_setup.tcl中创建Milkway数据库，新增判断逻辑

• 通过如下cmd，若重复建库不会报错