Verilog学习-07

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最新推荐文章于 2024-07-25 22:24:14 发布

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分类专栏： HDLBits练习文章标签：学习 fpga fpga开发

本文链接：https://blog.csdn.net/weixin_44814175/article/details/136689988

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本文分享了作者考研期间自学Verilog过程中遇到的两个实践问题：如何用Verilog实现一个计时器和一个饱和计数器。通过实例详细描述了这两个电路的工作原理和编程实现。

摘要由CSDN通过智能技术生成

考研上微电子入了材料坑，开始自学verilog

此文很多也是在其他优秀的博文中复制过来

（在此也非常感谢大家在网上分享的笔记）

仅为方便记录自己学习的笔记

习题链接：HDLBits

五、CS450

timer

Implement a timer that counts down for a given number of clock cycles, then asserts a signal to indicate that the given duration has elapsed. A good way to implement this is with a down-counter that asserts an output signal when the count becomes 0.

At each clock cycle:

If load = 1, load the internal counter with the 10-bit data, the number of clock cycles the timer should count before timing out. The counter can be loaded at any time, including when it is still counting and has not yet reached 0.
If load = 0, the internal counter should decrement by 1.

The output signal tc ("terminal count") indicates whether the internal counter has reached 0. Once the internal counter has reached 0, it should stay 0 (stop counting) until the counter is loaded again.

Below is an example of what happens when asking the timer to count for 3 cycles:

load是高电平的时候，存data的数据，当load变为低电平时，counter读取data数据开始递减直至为0，后tc转为高电平

module top_module(
	input clk, 
	input load, 
	input [9:0] data, 
	output tc
);	
    reg	[9:0]c;
    always@(posedge	clk)begin
        if(load)
            c	<=	data;
        else	if(c>0)
            c	<=	c-1;
    end
    assign	tc	=	(c==0)?1:0;

endmodule

counter 2bc

Build a two-bit saturating counter.

The counter increments (up to a maximum of 3) when train_valid = 1 and train_taken = 1. It decrements (down to a minimum of 0) when train_valid = 1 and train_taken = 0. When not training (train_valid = 0), the counter keeps its value unchanged.

areset is an asynchronous reset that resets the counter to weakly not-taken (2'b01). Output state[1:0] is the two-bit counter value.

说白了就是train_valid为低电平时，state保持；train_valid为高电平时，train_taken为高电平state递增最高至3，train_taken为低电平state递减最低至0；

异步复位areset，并且复位state状态为2’b01.

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output [1:0] state
);
    always@(posedge	clk	or	posedge	areset)begin 
        if(areset==1)
            state	<=	2'b01;
        else	if(train_valid==1)begin
            if(train_taken	&&	state<3)
                state	<=	state+1;
            else	if(!train_taken	&&	state>0)
                state	<=	state-1;
        end
     	else
          	state	<=	state;
    end

endmodule