Verilog学习-05

 考研上微电子入了材料坑，开始自学verilog

此文很多也是在其他优秀的博文中复制过来

（在此也非常感谢大家在网上分享的笔记） 

仅为方便记录自己学习的笔记

习题链接：HDLBits

三，电路

3.3，大规模电路

1000计数器

module top_module (
    input clk,
    input reset,
    output [9:0] q);

    always@(posedge	clk)begin
        if(reset==1)
            q	<=	0;
        else	begin
            if(q	==	10'b1111100111)
           	 	q	<=	0;
        	else
            	q	<=	q+1;
        end
    end

endmodule

4位移位寄存器和下行计数器

Build a four-bit shift register that also acts as a down counter. Data is shifted in most-significant-bit first when shift_ena is 1. The number currently in the shift register is decremented when count_ena is 1. Since the full system doesn't ever use shift_ena and count_ena together, it does not matter what your circuit does if both control inputs are 1 (This mainly means that it doesn't matter which case gets higher priority).

module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output [3:0] q);
    
    always@(posedge	clk)begin
        if(shift_ena==1)
            q	<=	{q[2:0],data};
        else	if(count_ena==1)
            q	<=	q-1;
    end
            
endmodule

FSM:序列1101识别器

Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Getting stuck in the final state is intended to model going to other states in a bigger FSM that is not yet implemented. We will be extending this FSM in the next few exercises.

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);
    parameter	s0=0,s1=1,s2=2,s3=3,s4=4;
    reg	[2:0]state,next;
    always@(posedge	clk)begin
        if(reset==1)
            state	<=	s0;
        else
            state	<=	next;
    end
    always@(*)begin
        case(state)
            s0:next=data?s1:s0;
            s1:next=data?s2:s0;
            s2:next=data?s2:s3;
            s3:next=data?s4:s0;
            default:next=s0;
        endcase
    end
    always@(posedge	clk)begin
        if(reset==1)
            start_shifting	<=	0;
        else	if(next==s4)
            start_shifting	<=	1;
    end
endmodule

FSM:开启移位寄存器

Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset).

module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);
   	parameter	s0=0,s1=1,s2=2,s3=3;
    reg	[1:0]state,next;
    always@(posedge	clk)begin
        if(reset==1)
            state	<=	s0;
        else
            state	<=	next;
    end
    always@(*)begin
        case(state)
            s0:next=s1;
            s1:next=s2;
            s2:next=s3;
            s3:next=s3;
            default:next=s0;
        endcase
    end
    always@(posedge	clk)begin
        if(reset==1)
            shift_ena	<=	1;
        else	if(state==s3)
            shift_ena	<=	0;
        else
            shift_ena	<=	1;
    end
endmodule

FSM:完整状态机

In this problem, implement just the finite-state machine that controls the timer. The data path (counters and some comparators) are not included here.

The serial data is available on the data input pin. When the pattern 1101 is received, the state machine must then assert output shift_ena for exactly 4 clock cycles.

After that, the state machine asserts its counting output to indicate it is waiting for the counters, and waits until input done_counting is high.

At that point, the state machine must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).

The state machine should reset into a state where it begins searching for the input sequence 1101.

Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once a 1101 pattern is detected, the FSM no longer looks at the data input until it resumes searching after everything else is done.

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
    parameter	s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6;//s0-s3检测data数据
    reg	[2:0]state,next,q;
    always@(posedge	clk)begin
        if(reset==1)
            state	<=	s0;
        else
            state	<=	next;
    end
    always@(*)begin
        case(state)
            s0:next=data?s1:s0;
            s1:next=data?s2:s0;
            s2:next=data?s2:s3;
            s3:next=data?s4:s0;
            s4:next=(q==3'b011)?s5:s4;
            s5:next=done_counting?s6:s5;
            s6:next=ack?s0:s6;
            default:next=s0;
        endcase
    end
    always@(posedge	clk)begin
        if(reset==1)
            q	<=	0;
        else	if(state==s4)begin
            if(q==3'b011)
            	q	<=	0;
        	else
            	q	<=	q+1;
        end
        else
            q	<=	q;
    end
    
    assign shift_ena =(state==s4)?1:0;
    assign counting  =(state==s5)?1:0;
    assign done 	 =(state==s6)?1:0;
    
endmodule

计时器

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
    parameter	s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6;
    reg	[3:0]state,next,countn,q,c0;//q是存data在1101后的数据，count计四个周期
    reg	[13:0]c;//计数,d16000=b11111010000000
    always@(posedge	clk)begin
        if(reset==1)
            state	<=	s0;
        else
            state	<=	next;
    end
    always@(*)begin
        case(state)
            s0:next=data?s1:s0;
            s1:next=data?s2:s0;
            s2:next=data?s2:s3;
            s3:next=data?s4:s0;
            s4:next=(countn==3)?s5:s4;
            s5:begin
                next=(c==(q+1)*1000-1)?s6:s5;
                case(c)
                    0:c0=q;
                    1000:c0=q-1;
                    2000:c0=q-2;
                    3000:c0=q-3;
                    4000:c0=q-4;
                    5000:c0=q-5;
                    6000:c0=q-6;
                    7000:c0=q-7;
                    8000:c0=q-8;
                    9000:c0=q-9;
                    10000:c0=q-10;
                    11000:c0=q-11;
                    12000:c0=q-12;
                    13000:c0=q-13;
                    14000:c0=q-14;
                    15000:c0=q-15;
                endcase
            end
            s6:next=ack?s0:s6;
            default:next=s0;
        endcase
    end
    always@(posedge	clk)begin
        if(reset==1)begin
            countn	<=	0;
            q	<=	0;
            c	<=	0;
        end
        else	if(state==s4)begin
            countn	<=	countn+1;
            q	<=	{q[3:0],data};
        end
        else	if(state==s5)begin
            c	<=	c+1;
            q	<=	q;
        end	
        else	begin
            countn	<=	0;
            q	<=	0;
            c	<=	0;
        end           
    end
         
    assign count	 =(state==s5)?c0:0;
    assign counting  =(state==s5)?1:0;
    assign done 	 =(state==s6)?1:0;

endmodule

开始没搞明白这个count输出是什么，后面搞明白了，就数计数多少次一直减一，但是后面还是报错，count输出d到c的时候，会变成4。后面再看看怎么改

（2024.03.12）