ubuntu下vcs仿真范例及问题处理

MiMiWho

已于 2024-06-10 19:38:22 修改

阅读量153

点赞数 1

文章标签： ubuntu fpga开发

于 2024-06-06 22:01:17 首次发布

本文链接：https://blog.csdn.net/weixin_44833870/article/details/139510765

版权

环境：Ubuntu
编写：verilog：vim
编译仿真：vcs

vim counter.v

module  counter(
input   clk,
input   rst,
output  reg     [5:0]   count
);
always  @(posedge       clk     or      negedge rst)
begin
        if(!rst)
                count <= 0;
        else
                count <= count + 1;
end
endmodule

vim tb_counter.v

module  tb_counter();
reg     clk,rst;
wire    [5:0]   counter;

counter u1(clk,rst,counter);
always #(5) clk = ~clk;

initial begin
        clk     <=      0;
        rst     <=      0;
        #20;
        rst     <=      1;
        #50;
        if(counter != 5)
                $display("tb counter finish.");
        else
                $display("You gotta the right result!");
        $finish;
end
`ifdef FSDB
        initial begin
                $fsdbDumpfile("tb.fsdb");
                $fsdbDumpvars;
        end
`endif

endmodule

问题报错处理：
直接用vcs编译会报错如下：

Makefile:109: recipe for target 'product_timestamp' failed
```powershell
vim makefile

改用gcc匹配版本即可。

com:
        vcs -full64     \
        -sverilog       \
        -cpp g++-4.8    \
        -cc gcc-4.8     \
        -LDFLAGS -Wl,--no-as-needed     \
        -f file.list    \
        +v2k    \
        -l com.log      \
        -debug_all+all  \
        -kdb    \
        -timescale=1ns/1ps      
sim:
        ./simv  \
        -l run.log      \
        -gui &

make

也可直接用命令：

vcs -R -full64 -cpp g++-4.8 -cc gcc-4.8 -LDFLAGS -Wl,--no-as-needed +v2k -fsdb +define+FSDB -sverilog counter.v tb_counter.v timescale.v -l run.log

问题二：

g++-4.8:error:unrecognize command line option '-no-pie'

修改vcs安装路径：~/synopsys/vcs_2018vo/vcs/O-2018.09-SP2/bin
将SNPS_VCS_INTERNAL_UBUNTU_PRE_LDFLAGS后面的-no-pie删除即可。
最后结果：

/synopsys/vcs_2018vo/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o -ldl  -lc -lm -lpthread -ldl 
../simv up to date
make[1]: Leaving directory '/home/hostname/uvmdemo/counter/csrc'
CPU time: 1.841 seconds to compile + .359 seconds to elab + .253 seconds to link
Verdi KDB elaboration done and the database successfully generated: 0 error(s), 0 warning(s)