数字跑表———具有暂停、清零功能
module paobiao6_14(clk,CLR,K2,PAUSE,data,sm_wei,sm_duan);
input clk;
input CLR;
input K2;
input PAUSE;
output [23:0]data;
output [5:0] sm_wei;//4位数码管的位选信号
output [7:0] sm_duan;//4位数码管共用的段选信号
//----------------------------------------------------------
//分频
integer clk_cnt;
reg clk_500Hz;
always @(posedge clk)
if(clk_cnt==32’d100000)
begin clk_cnt <= 1’b0; clk_500Hz <= ~clk_500Hz;end
else
clk_cnt <= clk_cnt + 1’b1;
//----------------------------------------------------------
//位控制
reg [5:0]wei_ctrl=6’b111110;
always @(posedge clk_500Hz)
wei_ctrl <= {wei_ctrl[4:0],wei_ctrl[5]};
//段控制
reg [3:0]duan_ctrl;
//----------------------------------------------------------
//分频 1Hz
reg clk_1Hz;
integer clk_1Hz_cnt;
always @(posedge clk)
if(clk_