【Verilog数字系统设计——数字跑表】
题目
1 编程实现一个数字跑表。该跑表模块端口至少应包括:
1.1 CLK: 时钟信号(测试时钟频率自己设定);
1.2 CLR: 异步复位信号;
1.3 START: 开始计时信号(异步使能);
1.4 PAUSE: 暂停计时信号(异步使能);
1.5 MSH,MSL: 百分之一秒的高位和低位;
1.6 SH,SL: 秒信号的高位和低位;
1.7 MH,ML: 分钟信号的高位和低位。。
2 要求完成程序编辑、编译、时序仿真;
3 实验提交Verilog设计文件(.v文件)、仿真波形截图文件打包,压缩包以自己的学号+姓名命名;
代码
module digital_watch(MH,ML,SH,SL,MSH,MSL,start,clk,clr);
input clk,clr,start;
output [3:0] MH,ML,SH,SL,MSH,MSL;
reg [3:0]MH,ML,SH,SL,MSH,MSL;
reg cin1,cin2;
//cin1 is MSH cin,cin2 is SH cin;
//judgement hundredth of a second
always @(posedge clk or negedge clr or negedge start)
begin
if(!clr)
begin
MSH<=4'b0;
MSL<=4'b0;
cin1<=1'b0;
end
else if(!start)
begin
if(MSL==9)
begin
MSL<=0;
if(MSH==9)
begin
MSH<=0;
cin1<=1;
end
else
MSH<=MSH+1;
end
else
begin
MSL<=MSL+1;
cin1<=0;
end
end
end
always @(posedge clk or posedge cin1 or negedge clr)
begin
if(!clr)
begin
SH<=4'b0;
SL<=4'b0;
cin2<=1'b0;
end
else if(cin1)
begin
if(SL==9)
begin
SL<=0;
if(SH==5)
begin
SH<=0;
cin2<=1;
end
else
SH<=SH+1;
end
else
begin
SL<=SL+1;
cin2<=0;
end
end
end
always @(posedge clk or posedge cin1 or negedge clr)
begin
if(!clr)
begin
MH<=4'b0;
ML<=4'b0;
end
else if(cin2)
begin
if(ML==9)
begin
ML<=0;
if(MH==5)
begin
MH<=0;
end
else
MH<=MH+1;
end
else
begin
ML<=ML+1;
end
end
end
endmodule
module digital_watch_test;
reg clk_t,clr_t,start_t;
wire [3:0]MSH_t,MSL_t,SH_t,SL_t,MH_t,ML_t;
digital_watch digital_watch(.MH(MH_t),.ML(ML_t),.SH(SH_t),.SL(SL_t),.MSH(MSH_t),.MSL(MSL_t),.start(start_t),.clk(clk_t),.clr(clr_t));
initial
begin
clk_t=0;
clr_t=1;
start_t=1;
#5
clr_t=0;
start_t=0;
#5
clr_t=1;
start_t=1;
end
always #10 clk_t=~clk_t;
endmodule