`timescale 1ns / 1ps
module tb();
//应该没有什么用处
reg Clk;
reg [31:0] addr = 0;
reg [63:0] readData [0:130-1];
reg [63:0] din;
wire [63:0] dout;
integer dout_file1;
initial begin
Clk = 0;
$readmemh("D:/CRCDin.txt",readData);
dout_file1=$fopen("D:/verilogwrite_frame.txt"); //打开所创建的文件
if(dout_file1 == 0)begin
$display ("can not open the file!"); //创建文件失败,显示can not open the file!
$stop;
end
end
worker worker(
.Clk(Clk),
.din(din),
.dout(dout)
);
always@(posedge Clk)begin
din<=readData[addr];
addr<=addr+1;
end
always
always @(posedge Clk)begin
$fdisplay(dout_file1,"%h",dout); //保存数据
end
endmodule