序列状态机（10010）--代码+testbench

序列状态机两段式写法：（两个always语句）
1 module check(clk,rst,x,out);
2 input clk;
3 input rst;
4 input x;
5 output out;
6 reg[3:0] current_state;
7 reg[3:0] next_state;
8 parameter S0=5’b0000,//0
9 S1=5’b0001,//1
10 S2=5’b0010,//10
11 S3=5’b0100,//100
12 S4=5’b1001,//1001
13 S5=5’b10010;
14
15 always@(posedge clk)
16 begin
17 if(rst)
18 current_state<=S0;
19 else
20 current_state<=next_state;
21 end
22 always@(current_state or x)
23 begin
24 case(current_state)
25 S0: begin
27 if(x1) next_state=S1;
28 else next_state=S0;
29 end
30 S1: begin
32 if(x0) next_state=S2;
33 else next_state=S1;
34 end
35 S2: begin
37 if(x0) next_state=S3;
38 else next_state=S1;
39 end
40 S3: begin
42 if(x1) next_state=S4;
43 else next_state=S0;
44 end
45 S4: begin
47 if(x0) next_state=S5;
48 else next_state=S1;
49 end
50 S5: begin
51 next_state=S0;
52 end
53 default: next_state=S0;
54 endcase
55 end
56 assign out=(current_stateS4&&x==0)?1:0;//输出
57 endmodule

testbench
`timescale 1ns/1ps
2 module tb();
5 reg clk;
6 reg rst;
7 reg x;
8 reg[11:0] data;
9 //
10 wire out;
11 //clock
12 initial begin
13 clk =0;
14 forever begin
15 clk=#20 ~clk;
16 end
17 end
18 initial begin
19 data = 12’b101100110010;
20 #2000 $finish;
21 end
22
23 //rst
24 initial begin
25 rst =1;
26 #100;
27 rst=0;
28 end
29
30
31 always@(posedge clk)
32 #2 data={data[10:0],data[11]};
33 assign x=data[11]; //激励的产生
34 check DUT(.clk(clk),
35 .rst(rst),
36 .x(x),
37 .out(out));
38
39
40 initial begin
41 $fsdbDumpfile(“tb_verdi.fsdb”);
42 $fsdbDumpvars(0,"+all");
43 end
44
45 endmodule