三段式状态机（附带testbench）

最新推荐文章于 2024-07-12 21:08:36 发布

成辰

最新推荐文章于 2024-07-12 21:08:36 发布

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文章标签： verilog 状态机

本文链接：https://blog.csdn.net/qq_44765998/article/details/108479222

版权

三段式状态机

module state_machine
(
input reset_p,
input clk_10k,
input flag_p,
input [7:0]data,
output out1
);
reg [1:0]cr_state;
reg [1:0]nx_state;
reg [2:0]count;
reg temp_out1;
assign out1=temp_out1;
parameter IDLE = 2'b00,START = 2'b01,WRITE = 2'b10,WRITEEND = 2'b11;
always@(posedge clk_10k)
begin
    if(reset_p)
        cr_state    <=  IDLE;
    else
        cr_state    <=  nx_state;
end

always@*
begin
    case(cr_state)
    IDLE:   begin
                if(flag_p)
                    nx_state    =   START;
                else
                    nx_state    =   IDLE;
            end
    START:  begin
                nx_state    =   WRITE;
            end
    WRITE:  begin
                if(count==3'd0)
                    nx_state    =   WRITEEND;
                else
                    nx_state    =   WRITE;
            end
    WRITEEND:   begin
                    nx_state    =   IDLE;
                end
    default nx_state = IDLE;
    endcase
end

always@(posedge clk_10k)
begin
    case(cr_state)
    IDLE:   begin
                temp_out1   <=  1'b0;
                count       <=  3'd0;
            end
    START:  begin
                temp_out1   <=  1'b0;
                count       <=  3'd7;
            end
    WRITE:  begin
                temp_out1   <=  data[count];
                count       <=  count-3'd1;
            end
    WRITEEND:   begin
                    temp_out1   <=  data[count];
                    count       <=  3'd0;
                end
    default:begin
                temp_out1   <=  temp_out1;
                count       <=  count;
            end
    endcase
end
endmodule

测试程序

module test(

    );
    reg reset_p;
    reg clk_10k;
    reg flag_p;
    reg [7:0]data;
    wire out1;
    initial
    begin
    reset_p=1'b0;
    clk_10k=1'b0;
    flag_p=1'b0;
    data[7:0]=8'b10110001;
    #25 reset_p=1'b1;
    #40 reset_p=1'b0;
    #60 flag_p=1'b0;
    #80 flag_p=1'b1;
    #90 flag_p=1'b0;
    end
    always #10 clk_10k=~clk_10k;
    state_machine state_machine
    (
    .reset_p(reset_p),
    .clk_10k(clk_10k),
    .flag_p(flag_p),
    .data(data),
    .out1(out1)
    );
endmodule