数字逻辑：23-61计数（加法）器（使用MAX+plus II 、Verilog语言 编写）

代码

module counter23_61(reset,clk,mid_H,mid_L,mid_L_cy);

    input reset,clk;
    output[3:0] mid_H,mid_L;
    output mid_L_cy;
    reg[3:0] mid_H,mid_L;
    wire mid_L_cy;
    assign mid_L_cy=(mid_L==4'd9)?1:0;
    always @ (posedge clk)
		begin
        	if(reset) mid_L<=4'd3;
            else if(mid_H==4'd6 & mid_L==4'd1) mid_L=4'd3;
        	else if(mid_L_cy==1) 
                 begin
                     if(mid_H==4'd6) mid_L<=4'd3;
                     else mid_L<=4'd0;
                 end
        	else mid_L<=mid_L+1;
    	end
    always @ (posedge clk)
		begin
        	if(reset) mid_H<=4'd2;
            else if(mid_H==4'd6 & mid_L==4'd1) mid_H=4'd2;
        	else if(mid_L_cy==1)
				begin
            		if(mid_H==4'd6) mid_H<=4'd2;
            		else mid_H<=mid_H+1;
        		end
        	else mid_H<=mid_H;
		end

endmodule

说明

1、修改了上次加法器的不足之处。实现了从“XX-XX”的加法器。