VCS issues && solutions(1)

Issue1：Deadloop（Infinite）Loops

• Syndrome: simulation hangs and time not change
• Diagnose:
  • add "+vcs+loopreport+number" to VCS compile option
  • add "+vcs+loopreport" or "+vcs+loopreport+N" to VCS runtime option
• Report:

  VCS Loop Detection: Switching loop detection algorithm ON at time <$time> delta-cycles exceeded the threshold-limit. Possible zero delay loop(s). The following files are generated: 1) loop-info-#.log // # = proc-id 2) loop-info-verbose-#.log

Above opiton add for debug not by default, which will affect compile/simulation speed.

Issue2: Bind interface failed

• Syndrome: Error-[VIPCBD] variable input ports cannot be driven
• Diagnose:
  • LRM: An implicit data type declaration implies a net unless the var keyword is used.(refer:LRM 23.2.2.3 Rules for determining port kind, data type, and direction)
  • But VCS infer implicit data type as varialbe,which not follow LRM.

module ma(input logic a); ... interface ma_if(output logic a_if); ... bind ma ma_if ma_if(.a_if(a));

• Solution:
  • add compile solution "-sv_net_ports" for compile option for two flows; add for both vlogan and vcs if three flows.
  • VCS description: Port declaration with implicit port kind follows the SystemVerilog LRM rules under the -sv_net_ports option.

Issue3: Undefine System Task call to $fsdbDumpvars

• Solution:
  • add environment variables: NOVAS_HOME and VERDI_HOME to verdi install home : setenv VERDI_HOME /tools/synopsys/verdi/u-2023.03-sp2 setenv NOVAS_HOME /tools/synopsys/verdi/u-2023.03-sp2
  • add compile option "-debug_acess+all"

Issue4: No ENV/DUT hierarchy when open fsdb waveform

• Solution
  • add compile opiton "-kdb"
  • open waveform command: verdi -nologo -ssf xx.fsdb