Verilog刷题HDLBits——Cs450/history shift
题目描述
![在这里插入图片描述](https://i-blog.csdnimg.cn/blog_migrate/cbace06eb1ff12a353393da1b51348c8.png)
代码
module top_module(
input clk,
input areset,
input predict_valid,
input predict_taken,
output [31:0] predict_history,
input train_mispredicted,
input train_taken,
input [31:0] train_history
);
reg [31:0] shift_reg;
always@(posedge clk or posedge areset)
begin
if(areset)
shift_reg<=31'b0;
else if(train_mispredicted)
shift_reg<={train_history[30:0],train_taken};
else if(predict_valid)
shift_reg<={shift_reg[30:0],predict_taken};
else
shift_reg<=shift_reg;
end
assign predict_history = shift_reg;
endmodule
结果
![在这里插入图片描述](https://i-blog.csdnimg.cn/blog_migrate/9f9dc63a69da7107dc78eb340691c869.png)