IC验证学习笔记（AHB-RAM）00基本框架

目的是开发AHB master agent

先构建起各部分的框架

PACKAGE：包含各个文件

        `ifndef ·define ·endif作用是防止重复调用文件（大写）

package都要加  import uvm_pkg::*;
                          `include "uvm_macros.svh"  这两行

`ifndef LVC_AHB_PKG_SV
`define LVC_AHB_PKG_SV

package lvc_ahb_pkg;
  import uvm_pkg::*;
  `include "uvm_macros.svh"

  `include "lvc_ahb_defines.svh"
  `include "lvc_ahb_types.sv"
  `include "lvc_ahb_transaction.sv"  
  `include "lvc_ahb_sequencer.sv"  
  `include "lvc_ahb_driver.sv"  
  `include "lvc_ahb_monitor.sv"  
  `include "lvc_ahb_master_transaction.sv"  
  `include "lvc_ahb_master_driver.sv"  
  `include "lvc_ahb_master_monitor.sv"  
  `include "lvc_ahb_master_sequencer.sv"  
  `include "lvc_ahb_master_agent.sv"  

endpackage


`endif // LVC_AHB_PKG_SV

transaction:

`ifndef LVC_AHB_TRANSACTION_SV
`define LVC_AHB_TRANSACTION_SV


class lvc_ahb_transaction extends uvm_sequence_item;
  `uvm_object_utils_begin(lvc_ahb_transaction)
  `uvm_object_utils_end

  function new(string name = "lvc_ahb_transaction");
    super.new(name);
  endfunction


endclass

`endif // LVC_AHB_TRANSACTION_SV

driver、secquencer、master_driver、master_sequencer都是参数化类：

`ifndef LVC_AHB_DRIVER_SV
`define LVC_AHB_DRIVER_SV

class lvc_ahb_driver #(type REQ = lvc_ahb_transaction, type RSP = REQ) extends uvm_driver #(REQ, RSP);
  `uvm_component_utils(lvc_ahb_driver)

  function new(string name = "lvc_ahb_driver", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
  endfunction

  function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
  endfunction

  task run_phase(uvm_phase phase);
    super.run_phase(phase);
  endtask

endclass


`endif // LVC_AHB_DRIVER_SV

monitor、master_monitor、agent、master_agent:

`ifndef LVC_AHB_MASTER_AGENT_SV
`define LVC_AHB_MASTER_AGENT_SV

class lvc_ahb_master_agent extends uvm_agent;
  `uvm_component_utils(lvc_ahb_master_agent)

  function new(string name = "lvc_ahb_master_agent", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
  endfunction

  function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
  endfunction

  task run_phase(uvm_phase phase);
    super.run_phase(phase);
  endtask

endclass


`endif // LVC_AHB_MASTER_AGENT_SV

AHB interface：

`ifndef LVC_AHB_IF_SV
`define LVC_AHB_IF_SV

interface lvc_ahb_if;

endinterface

顶层环境 interface:

`ifndef RKV_AHBRAM_IF_SV
`define RKV_AHBRAM_IF_SV

interface rkv_ahbram_if;

endinterface

顶层环境package：

`ifndef RKV_AHBRAM_PKG_SV
`define RKV_AHBRAM_PKG_SV

package rkv_ahbram_pkg;
  import uvm_pkg::*;
  `include "uvm_macros.svh"
  import lvc_ahb_pkg::*;

endpackage

tb：

module rkv_ahbram_tb;
  import uvm_pkg::*;
  `include "uvm_macros.svh"
  import rkv_ahbram_pkg::*;

  ahb_blockram_32 dut();

  initial begin
    //run_test();
  end


endmodule