vscode_verilog代码片段分享

秦仲洋X
已于 2023-03-14 16:35:14 修改
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文章标签： fpga开发
于 2023-03-14 16:26:43 首次发布
本文链接：https://blog.csdn.net/weixin_48086808/article/details/129531705
版权
{
	//		用名字对每个用户片段下定义，并具有前缀、主体和描述。
	//		前缀用于触发代码片段，用户片段正文将被展开和插入。
	//		我的习惯是不同always之间,全部不加空行,但是要加上注释
	//		普通的奇怪字符加一个反斜杠\可以不被误会是转义字符
	//		$前面加两个\\变成\\$可以不被误会是转义字符

	//*		${1:名字}表示第一个光标插入位置,${2:名字}表示第二个光标插入位置,依次类推
	//*		序号一样的$可以同时编辑,${0:名字}表示tab的最终位置

///
//模板解释
	//这个位置是片段的名字
	"Print to console": {
		//前缀,就是打哪些词能调用这个用户片段
		"prefix": "log",
		//body就是我们要插入的用户片段,每一行都是一个json格式的句子
		//注意:双引号需要加上转义符
		//注意:还有光标的使用
		"body": [
			"console.log('$1');",
			"$2"
		],
		//描述.这个用来提示这个用户片段的功能
		"description": "Log output to console"
	},//上一个片段写完之后,最后面要加个逗号.
//
	"D触发器": {
		"prefix": "DFF",
		"body": [
			"always  @(posedge clk or negedge rst_n)begin ",
			"    if(rst_n==1'b0)begin ",
			"        q <= 0; ",
			"    end ",
			"    else begin ",
			"        q <= d; ",
			"    end ",
			"end"
		],
		"description": "D触发器的标准写法"
	},//上一个片段写完之后,最后面要加个逗号.

	"模块框架": {
		"prefix": "module",
		"body": [
			"//${0:注释}",
			"module ${1:模块名}(",
			" //输入信号定义",
			"    input  wire   clk    ,//时钟",
			"    input  wire   rst_n  ,//低电平复位",
			"    //输出信号定义",
			"    output reg   [${2:DATA_W-1}:0] ${3:out} ",
			"    );",
			"    ",
			"    //参数定义",
			"    ${4:参数名}      DATA_W = ${5:8};",
			"    //中间信号定义",
			"    reg                 ${9:signal1};",
			"    ",
			"    //组合逻辑写法",
			"    always@(*)begin",
			"       $10           ",
			"    end",
			"    ",
			"    //时序逻辑写法",
			"    always@(posedge clk or negedge rst_n)begin",
			"    if(rst_n==1'b0)begin",
			"       $11             ",
			"    end",
			"    else begin",
			"       $12             ",
			"    end",
			"end",
			"",
			"endmodule"
		],
		"description": "模块框架"
	},
//
"时序逻辑(一个条件)": {
	"prefix": "shixu1",
	"body": [
		"//${0:注释}",
		"always  @(posedge clk or negedge rst_n)begin",
		"  if(rst_n==1'b0)//低电平复位",
		"    ${1:信号} <= 0;//时序逻辑使用非阻塞赋值",
		"  else if(${2:激励})",
		"    ${3:响应}",
		"end"
	],
	"description": "时序逻辑(一个条件)"
},
//
"时序逻辑(两个条件)": {
	"prefix": "shixu2",
	"body": [
		"//${0:注释}",
		"always  @(posedge clk or negedge rst_n)begin",
		"  if(rst_n==1'b0)begin",
		"  ${1:信号} = 0;",               
		"  end",
		"  else if(${2:激励})begin",
		"  ${3:响应}",
		"  end",
		"  else if(${4:激励})begin",
		"  ${5:响应}",
		"  end",
		"end"
	],
	"description": "时序逻辑(两个条件)"
},
//
"时序逻辑(三个条件)": {
	"prefix": "shixu3",
	"body": [
		"//${0:注释}",
		"always  @(posedge clk or negedge rst_n)begin",
		"  if(rst_n==1'b0)begin",
		"  ${1:信号} = 0;",
		"  end",
		"  else if(${2:激励})begin",
		"  ${3:响应}",
		"  end",
		"  else if(${4:激励})begin",
		"  ${5:响应}",
		"  end",
		"  else if(${6:激励})begin",
		"  ${7:响应}",
		"  end",
		"end"
	],
	"description": "时序逻辑(三个条件)"
},
/
"组合逻辑(无条件)": {
	"prefix": "ZuHe0",
	"body": [
		"//${0:注释}",
		"always  @(*)begin",
		"${1:响应};",
		"end "
	],
	"description": "组合逻辑(无条件)"
},
/
"组合逻辑(一个条件)": {
	"prefix": "ZuHe1",
	"body": [
		"//${0:注释}",
		"always  @(*)begin",
		"  if(${1:激励})begin",
		"     ${2:响应};",
		"  end",
		"  else begin",
		"     ${5:响应};",
		"  end",
		"end",
		""
	],
	"description": "组合逻辑(一个条件)"
},
/
"组合逻辑(两个条件)": {
	"prefix": "ZuHe2",
	"body": [
		"//${0:注释}",
		"always  @(*)begin",
		"  if(${1:激励})begin",
		"     ${2:响应};",
		"  end",
		"  else if(${3:激励})begin",
		"     ${4:响应};",
		"  end",
		"  else begin",
		"     ${5:响应};",
		"  end",
		"end",
		""
	],
	"description": "组合逻辑(两个条件)"
},
/
"计数器": {
	"prefix": "jishuqi",
	"body": [
		"//${0:注释}",
		"always @(posedge clk or negedge rst_n)begin",
		"    if(!rst_n)begin",
		"        ${1:计数器名称cnt} <= 0;//按下复位键,计数器清零",
		"    end",
		"    else if(add_cnt)begin//加一条件满足",
		"    if(end_cnt)//结束条件满足则清零",
		"        ${1:计数器名称cnt} <= 0;",
		"    else",
		"        ${1:计数器名称cnt} <= ${1:计数器名称cnt} + 1;//否则计数加1",
		"    end",
		"end",
		"",
		"assign add_cnt = ${2:加一条件的产生};//加一条件的连线       ",
		"//表示计数器计数到计满值产生结束条件 ",
		"assign end_cnt = add_cnt && ${1:计数器名称cnt}== ${3:计满值}-1;  ",
		"",
		""
	],
	"description": "计数器"
},
/
"四段式状态机": {
	"prefix": "zhuangtaiji",
	"body": [
		"//${0:四段式状态机}",
		"//第一段：同步时序always模块，格式化描述次态寄存器迁移到现态寄存器(不需更改）",
		"always@(posedge clk or negedge rst_n)begin",
		"    if(!rst_n)begin",
		"    state_c <= IDLE;",
		"    end",
		"    else begin",
		"    state_c <= state_n;",
		"    end",
		"end",
		"//第二段：组合逻辑always模块，描述状态转移条件判断",
		"always@(*)begin",
		"    case(state_c)",
		"        ${1:IDLE}:begin//状态",
		"            if(idl2s1_start)begin",
		"                state_n = S1;//状态1",
		"            end",
		"            else begin",
		"                state_n = state_c;",
		"            end",
		"            end",
		"",
		"            S1:begin",
		"            if(s12s2_start)begin",
		"                state_n = S2;//状态2",
		"            end",
		"            else begin",
		"                state_n = state_c;",
		"            end",
		"            end",
		"",
		"            S2:begin",
		"            if(s22s3_start)begin",
		"                state_n = S3;//状态3",
		"            end",
		"            else begin",
		"                state_n = state_c;",
		"            end",
		"            end",
		"            default:begin",
		"                state_n = IDLE;",
		"        end",
		"    endcase",
		"end",
		"//第三段：设计转移条件",
		"assign idl2s1_start  = state_c==IDLE  && ;",
		"assign s12s2_start   = state_c==S1    && ;",
		"assign s22s3_start   = state_c==S2    && ;",
		"//第四段：同步时序always模块，格式化描述寄存器输出（可有多个输出）",
		"always  @(posedge clk or negedge rst_n)begin",
		"    if(!rst_n)begin",
		"    out1 <=1'b0      //初始化",
		"end",
		"else if(state_c==S1)begin",
		"    out1 <= 1'b1;",
		"end",
		"else begin",
		"    out1 <= 1'b0;",
		"end",
		"end ",
		""
	],
	"description": "四段式状态机"
},
/
"状态机_三段式_四个状态": {
	"prefix": "ztj_三段式_四状态_正点原子",
	"body": [
		"//本片段完全手打,做好失败的准备",
		"//步骤1:状态空间定义",
		"//设置状态空间,采用独热码译码逻辑简单",
		"parameter    ${1:状态1} = 4'b1000;",
		"parameter    ${2:状态2} = 4'b0100;",
		"parameter    ${3:状态3} = 4'b0010;",
		"parameter    ${4:状态4} = 4'b0001;",
		"//内部变量,用于步骤2状态跳转",
		"reg [3:0]    current_state;",
		"reg [3:0]    next_state;",
		"",
		"//步骤2:状态跳转,固定写法,一直在跳转状态(时序逻辑)",
		"always  @(posedge clk or negedge rst_n)begin",
		"  if(rst_n==1'b0)",
		"        current_state <= ${1:状态1};",
		"  else ",
		"        current_state <= next_state;",
		"end",
		"",
		"//步骤3:下一个状态判断(组合逻辑)",
		"//敏感信号表:所有的右边表达式中的变量以及if、 case条件中的变量,可以用*代替",
		"always @(current_state or input_signal) begin",
		"    case (current_state)",
		"        ${1:状态1}:begin",
		"            if (${1:状态1}结束条件) begin",
		"                next_state = ${2:状态2};//${1:状态1}结束,进入${2:状态2}",
		"            end else begin//If/else要配对以避免latch的产生",
		"                next_state = ${1:状态1};//没有满足${1:状态1}结束条件,依旧是${1:状态1}状态",
		"            end",
		"        end  ",
		"        ${2:状态2}:begin",
		"            if (${2:状态2}结束条件) begin",
		"                next_state = ${3:状态3};//${2:状态2}结束,进入${3:状态3}",
		"            end else begin",
		"                next_state = ${2:状态2};//没有满足${2:状态2}结束条件,依旧是${2:状态2}状态",
		"            end",
		"        end  ",
		"        ${3:状态3}:begin",
		"            if (${3:状态3}结束条件) begin",
		"                next_state = ${4:状态4};//${3:状态3}结束,进入${4:状态4}",
		"            end else begin",
		"                next_state = ${3:状态3};//没有满足${3:状态3}结束条件,依旧是${3:状态3}状态",
		"            end",
		"        end  ",
		"        ${4:状态4}:begin",
		"            if (${4:状态4}结束条件) begin",
		"                next_state = 状态0;//${4:状态4}结束,进入状态0",
		"            end else begin",
		"                next_state = ${4:状态4};//没有满足${4:状态4}结束条件,依旧是${4:状态4}状态",
		"            end",
		"        end  ",
		"        default:next_state = ${1:状态1};//其他情况,next_state默认为${1:状态1}",
		"    endcase",
		"end",
		"",
		"//步骤4:目的状态下的动作",
		"wire ${5:目的动作};//目的状态时执行的动作",
		"//${0:第三个 always 涉及时序则用时序逻辑完成,纯逻辑则用组合逻辑完成}",
		"//组合逻辑",
		"always @(current_state) begin",
		"    if (current_state = ${6:目的状态}) begin",
		"        ${5:目的动作} = 1;//在目的状态执行${5:目的动作}动作",
		"    end else begin",
		"        ${5:目的动作} = 0;",
		"    end",
		"end",
		"//时序逻辑",
		"always @(posedge clk or negedge rst_n) begin",
		"    if (rst_n==1'b0) begin",
		"        ${5:目的动作} <= 0;",
		"    end else if (${6:目的状态}) begin",
		"        ${5:目的动作} <= 1;//在目的状态执行${5:目的动作}动作",
		"    end else begin",
		"        ${5:目的动作} <= 0;",
		"    end",
		"end"
	],
	"description": "四个步骤写出来的三段式状态机,拥有四个状态,第三个always根据实际需求编写"
},
/
"测试模块": {
	"prefix": "ceshitb",
	"body": [
		"`timescale 1 ns/1 ns",
		"module ${1:测试模块名}();",
		"    //时钟和复位",
		"    reg clk  ;",
		"    reg rst_n;",
		"    //uut的输入信号",
		"    reg[3:0]  ${2:din0}  ;",
		"    reg       ${3:din1}  ;",
		"    //uut的输出信号",
		"    wire      ${4:dout0};",
		"    wire[4:0] ${5:dout1};",
		"    //时钟周期，单位为ns，可在此修改时钟周期。",
		"    parameter ${6:时钟周期,单位ns}    = ${7:20};",
		"    //复位时间，此时表示复位3个时钟周期的时间。",
		"    parameter ${8:复位时间} = ${9:3} ;",
		"    //待测试的模块例化",
		"    ${10:例化名} ${10:例化名}(",
		"    .clk          (${11:clk  }), ",
		"    .rst_n        (${12:rst_n}),",
		"    .din0         (${13:din0 }),",
		"    .din1         (${14:din1 }),",
		"    .dout0        (${15:dout0}),",
		"    .dout1        (${16:dout1})",
		"    );",
		"    //生成本地时钟50M",
		"    initial begin",
		"        clk = 0;",
		"        forever",
		"        #(CYCLE/2)",
		"        clk=~clk;",
		"    end",
		"    //产生复位信号",
		"    initial begin",
		"        rst_n = 1;",
		"        #2;",
		"        rst_n = 0;",
		"        #(CYCLE*RST_TIME);",
		"        rst_n = 1;",
		"    end",
		"    //输入信号din0赋值方式",
		"    initial begin",
		"        #1;",
		"        //赋初值",
		"        din0 = 0;",
		"        #(10*CYCLE);",
		"        //开始赋值",
		"    end",
		"    //输入信号din1赋值方式",
		"    initial begin",
		"        #1;",
		"        //赋初值",
		"        din1 = 0;",
		"        #(10*CYCLE);",
		"        //开始赋值",
		"    end",
		"endmodule   ",
		""
	],
	"description": "测试文件"
},
/***************************自己写的部分**********************************/
"测试时钟": {
	"prefix": "shizhong_tb",
	"body": [
		"//测试时钟,#${1:5}ns翻转一次",
		"initial",
		"begin",
		"    clk = 1'b0;",
		"    forever #${1:5} clk = ~clk;",
		"end"
	],
	"description": "tb文件的时钟生成"
},
/
"测试复位": {
	"prefix": "fuwei_tb",
	"body": [
		"//全局复位",
		"initial",
		"begin",
		"    rst_n = 1'b0;",
		"    repeat(${1:时钟延时数目}) @(posedge clk);",
		"    //${1:时钟延时数目}个时钟上升沿之后产生复位",
		"    rst_n = 1'b1;",
		"end"
	],
	"description": "测试模块的全局复位"
},
/
"电平变化": {
	"prefix": "dianpingbianhua",
	"body": [
		"reg                             ${2:临时寄存器};//r代表寄存的意思",
		"",
		"always @(posedge clk)",
		"begin",
		"    if(rst_n == 1'b0)",
		"        ${2:临时寄存器} <= 1'b0;",
		"    else",
		"        ${2:临时寄存器} <= ${1:待监测信号};",
		"end",
		"",
		"wire                            ${3:电平上升标志信号};",
		"wire                            ${4:电平下降标志信号};",
		"",
		"assign ${3:电平上升标志信号} = ~${2:临时寄存器} &  ${1:待监测信号};",
		"assign ${4:电平下降标志信号} =  ${2:临时寄存器} & ~${1:待监测信号};"
	],
	"description": "经典的电平变化监测函数.作用是检测 post_img_vsync 的上升沿和下降沿。"
},

/
"读取输出值tb": {
	"prefix": "duqushuchuzhi_tb",
	"body": [
		"",
		"// 灰度值输出并且保存到txt",
		"integer file;// integer关键字用于声明整型变量,可以用于存储整数类型的数据.file作用相当于临时程序名",
		"initial begin",
		"    //创建文件${2:文件名},(正斜杠路径),w表示写入模式",
		"    file = \\$fopen(\"${1:文件路径}/${2:文件名}\",\"w\");",
		"end",
		"",
		"initial begin",
		"    #${3:延迟时钟数}; // 延迟 ${3:延迟时钟数} 个时钟周期，等待仿真稳定",
		"    repeat (481*485) begin",
		"        \\$fwrite(file,\"%d\\n\",${4:输出变量名});",
		"        #10; // 延迟 1 个时钟周期，等待信号更新",
		"    end",
		"    \\$fclose(file);",
		"end"
	],
	"description": "可以用于读取仿真模块的一个输出值,并保存到文本中"
},
/
"延迟同步": {
	"prefix": "yanchitongbu_位宽=1",
	"body": [
		"//*******位宽=1,通过不同宽度寄存器达到延迟信号目的****************",
		"//因为输入信号可能会在不同的时钟周期上升沿到达，需要使用同步电路来确保正确处理这些信号",
		"//延迟同步信号,这些信号[供后续其他always块电路使用]",
		"reg             [2:0]           ${3:需延迟信号1寄存器};//与原信号区别是位数不同",
		"reg             [2:0]           ${4:需延迟信号2寄存器};",
		"reg             [2:0]           ${6:其他需延迟信号寄存器};",
		"//列,行,边缘信号,同步功能",
		"always @(posedge clk or negedge rst_n)",
		"begin",
		"    if(!rst_n)",
		"    begin",
		"        ${3:需延迟信号1寄存器} <= 3'b0;",
		"        ${4:需延迟信号2寄存器}  <= 3'b0;",
		"        matrix_edge_flag_r1 <= 3'b0;",
		"    end",
		"    else",
		"    begin",
		"        //${1:需延迟信号1},${2:需延迟信号2}等信号是我们需要延迟的信号,[已经在外部定义好了]",
		"        //通过依次向左移动达到将信号延迟3拍的作用",
		"        ${3:需延迟信号1寄存器} <= {${3:需延迟信号1寄存器}[1:0],${1:需延迟信号1}};",
		"        ${4:需延迟信号2寄存器} <= {${4:需延迟信号2寄存器}[1:0],${2:需延迟信号2}};",
		"        //边缘信号也是延迟三拍,用或的写法也可以",
		"        ${6:其他需延迟信号寄存器} <= {${6:其他需延迟信号寄存器}[1:0],${5:其他信号1} | ${5:其他信号2} | ${5:其他信号3} | ${5:其他信号4}};",
		"    end",
		"end",
		"//**********************************************************"
	],
	"description": "通过定义寄存器的方法,逐次移动信号值,使得原一位宽信号以多位宽寄存器的方式存在,后续电路可以调用这个信号的首位数据,达到信号同步延迟的目的"
},
/
"延迟同步_位宽>1": {
	"prefix": "yanchitongbu_位宽>1",
	"body": [
		"//********位宽>1,通过用数组寄存器延迟三拍时间后像素写入*********",
		"//[0:2]表示这个寄存器是一个三元素的一维数组寄存器",
		"reg             [7:0]           ${2:需延迟外部信号寄存器}       [0:2];",
		"always @(posedge clk)",
		"begin",
		"    //${1:需延迟外部信号} 是我们需要延迟的信号,[已经在外部定义好了]",
		"    //通过依次向左赋值,达到将信号延迟三拍的作用",
		"    ${2:需延迟外部信号寄存器}[0] <= ${1:需延迟外部信号};//赋值给 ${2:需延迟外部信号寄存器} 数组寄存器的第一个元素",
		"    ${2:需延迟外部信号寄存器}[1] <= ${2:需延迟外部信号寄存器}[0];",
		"    ${2:需延迟外部信号寄存器}[2] <= ${2:需延迟外部信号寄存器}[1];",
		"end"
	],
	"description": "通过定义数组寄存器的方法,逐次赋值信号值,使得原多位宽信号以数组元素寄存器的方式存在,后续电路可以调用这个信号的首位元素,达到信号同步延迟的目的"
},
/
"log2": {
	"prefix": "log2",
	"body": [
		"function integer funclog2;",
		"input   integer value;",
		"begin",
		"   value = value-1;",
		"   for (funclog2 = 0; value>0; funclog2 = funclog2+1) begin",
		"       value = value>>1;",
		"       end",
		"end",
		"",
		"endfunction"
	],
	"description": "log2"
},
/
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}