vscode verilog插件代码段配置

{
“module with parameters”: {
“prefix”: [“paramod”, “module #”],
“body”: [
“module KaTeX parse error: Expected 'EOF', got '#' at position 16: {1:moduleName} #̲(", "\t{2:parameters}”,
“) (”,
“\t${3:ports}”,
“);”,
“\t$0”,
“endmodule”
],
“description”: “Insert a module with parameter”
},
“module without parameters”: {
“prefix”: “module”,
“body”: [
“module KaTeX parse error: Undefined control sequence: \t at position 24: …eName} (", "\̲t̲{2:ports}”,
“);”,
“\tKaTeX parse error: Expected 'EOF', got '}' at position 79: …ut parameter" }̲, "instantiate…{1:mod_name} $2:instanc{e}_{n}ame(${3:.}$0);"
],
“description”: "set module, mod i0 (.);”
},
“always”: {
“prefix”: [“al”, “always”],
“body”: [
“always @($1) begin”,
“\t$2”,
“end”
],
“description”: “Insert an always block”
},
“alwaysposclk”: {
“prefix”: [“alclk”, “alwaysposclk”],
“body”: [
“always @(posedge clk $1) begin”,
“\t$2”,
“end”
],
“description”: “always @(posedge clk)”
},
“alwaysnegclk”: {
“prefix”: [“alnegclk”, “alwaysnegclk”],
“body”: [
“always @(negedge clk $1) begin”,
“\t$2”,
“end”
],
“description”: “always @(negedge clk)”
},
“begin/end”: {
“prefix”: “begin”,
“body”: [
“begin”,
“\t$1”,
“end”
],
“description”: “Insert a begin … end block”
},
“end”: {
“prefix”: “end”,
“body”: “end”,
“description”: “Insert end keyword”
},
“initial”: {
“prefix”: “initial”,
“body”: [
“initial begin”,
“\tKaTeX parse error: Expected 'EOF', got '}' at position 61: …egin ... end" }̲, "case": { …{1:param})”,
“\t$2: $3”,
“\tdefault: KaTeX parse error: Expected 'EOF', got '}' at position 63: … ... endcase" }̲, "casex": { …{1:param})”,
“\t$2: $3”,
“\tdefault: KaTeX parse error: Expected 'EOF', got '}' at position 64: … ... endcase" }̲, "casez": { …{1:param})”,
“\t$2: $3”,
“\tdefault: $4”,
“endcase”
],
“description”: “casez () … endcase”
},
“reg”: {
“prefix”: “reg”,
“body”: [
“reg $1;”
],
“description”: “reg reg_name;”
},
“regarray”: {
“prefix”: [“regarray”, “reg [”],
“body”: [
“reg [$1:$2] $3;”
],
“description”: “reg [N:0] reg_name;”
},
“regmemory”: {
“prefix”: [“regmemory”,“memory”],
“body”: [
“reg [$1:$2] $3 [$4:$5];”
],
“description”: “reg [N:0] reg_name [0:M];”
},
“wire”: {
“prefix”: “wire”,
“body”: [
“wire $1;”
],
“description”: “wire wire_name;”
},
“wirearray”: {
“prefix”: [“wirearray”, “wire [”],
“body”: [
“wire [$1:$2]